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将层次结构传递到 Verilog 模块

[英]Passing hierarchy into a Verilog module

I have a "watcher" module that is currently using global hierarchies inside it.我有一个“观察者”模块,它目前在其中使用全局层次结构。 I need to instantiate a second instance of this with a second global hierarchy.我需要用第二个全局层次结构实例化这个的第二个实例。

Currently:目前:

module watcher;
wire sig = `HIER.sig;
wire bar = `HIER.foo.bar;
...
endmodule

watcher w; // instantiation

Desired:期望:

module watcher(input base_hier);
wire sig = base_hier.sig;
wire bar = base_hier.foo.bar;
...
endmodule

watcher w1(`HIER1); // instantiation
watcher w2(`HIER2); // second instantiation, except with a different hierarchy

My best idea is to use vpp (the Verilog preprocessor) to brute-force generate two virtually-identical modules (one with each hierarchy), but is there a more elegant way?我最好的想法是使用 vpp(Verilog 预处理器)蛮力生成两个几乎相同的模块(每个层次结构一个),但有没有更优雅的方法?

My preference is to have a single module (or a small number of modules) in your testbench that contains all your probes but no other functionality.我的偏好是在您的测试平台中有一个模块(或少量模块),其中包含所有探针但没有其他功能。 All other modules in your testbench that require probes then connect to that "probe module".测试台中需要探针的所有其他模块然后连接到该“探针模块”。 Use SystemVerilog interfaces in preference to raw wires if that's an option for you.如果您愿意,请优先使用 SystemVerilog 接口而不是原始电线。 This circumvents your problem since no watcher will require global hierarchies and your testbench on the whole will be considerably easier to maintain.这绕过了您的问题,因为没有观察者需要全局层次结构,并且您的测试平台总体上将更容易维护。 See the Law of Demeter . 见得墨忒耳法则

Alternatively... (but this puts hierarchy in your instantiations...)或者......(但这会将层次结构放入您的实例中......)

module watcher(sig, bar);
  input sig;
  input bar;
...
endmodule

watcher w1(`HIER1.sig, `HIER1.foo.bar); // instantiation
watcher w2(`HIER2.sig, `HIER2.foo.bar); // second instantiation, except with a different hierarchy

Subsequently you can also:随后,您还可以:

`define WATCHER_INST(NAME, HIER) watcher NAME(HIER.sig, HIER.foo.sig)

`WATCHER_INST(w1, `HIER1);
`WATCHER_INST(w2, `HIER2);

Can you use the SystemVerilog bind keyword to bind the module into every hierarchy that requires it?您可以使用 SystemVerilog bind关键字将模块绑定到需要它的每个层次结构中吗? (This requires that you use SystemVerilog, and have a license for a simulator.) (这要求您使用 SystemVerilog,并拥有模拟器许可证。)

Using bind is like instantiating a module in the normal way, except that you provide a path to hierarchy into which the module is "remotely" instantiated:使用 bind 就像以正常方式实例化一个模块,只是您提供了一个层次结构的路径,模块被“远程”实例化到该层次结构中:

bind top.my.hier my_module instance_name(.*);
bind top.my_other.hier my_module instance_name(.*);

Even better: assume that each hierarchy that you are binding into is a separate instance of the same module.更好的是:假设您绑定到的每个层次结构都是同一模块的单独实例。 Then:然后:

bind remote_module my_module instance_name(.*);

This binds your module into every instance of the target, no matter where it is in the design.这会将您的模块绑定到目标的每个实例中,无论它在设计中的哪个位置。 This is very powerful if your module is a verification checker.如果您的模块是验证检查器,这将非常强大。

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