I am using Cortex-A15-Cortex-A7 big.LITTLE arch soc.
In case of big.LITTLE processor's bL_head.S (in case of LITTLE initialization), MRC instruction is used as follows :-
mrc p15, 0, r0, c0, c0, 5
Now, as per the MRC instruction detail,
MRC{cond} coproc, opcode1, Rd, CRn, CRm{, opcode2}
opcode2
is an optional coprocessor-specific opcode.
In basically all ARM processors, Coprocessor 15 is used for controlling various system functions of the current core. It does not refer to other processors in a multi-processor cluster. You can find the actual definitions of the CP15 registers in the core-specific Technical Reference Manual (TRM)
For example, looking up the combination you mention in the summary table of the Cortex-A7 TRM, we can see that it is MPIDR
(Multiprocessor Affinity Register). And in fact, if you follow the link to the detailed description, you'll see exactly this instruction:
To access the MPIDR, read the CP15 registers with:
MRC p15, 0, <Rt>, c0, c0, 5; Read Multiprocessor Affinity Register
In your case, <Rt>
is R0
. It is set to the value of MPIDR read from the hidden core register, and you can then interpret it as described in the TRM.
BTW, the specific combination of Opcode1, CRm, CRn and Opcode2 is processor-specific, but many of them are shared among the related cores. So in general you don't necessarily have to consult the TRM of the exact core you have, though of course it works best.
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