I am writing a simple flipflop module in verilog and I am trying to write a top level module in instantiate my flipflop module and simulate it in ModelSim.
Here is my code below,
module flipflop(clck,D,Q);
input clck,D;
output Q;
wire R,S,S_g,R_g,Qa,Qb;
assign R = ~D;
assign S = D;
nand(S_g,S,clck);
nand(R_g,R,clck);
nand(Qa,S_g,Qb);
nand(Qb,R_g,Qa);
assign Q = Qa;
endmodule
module TopLevel();
reg clck;
reg Q;
wire D;
flipflop p1(clck,D,Q);
always begin
#5 clck <=1;
#5 clck <=0;
end
endmodule
When I compile this code it runs fine, but when I try to simulate it, I get the following error:
# ** Error: (vsim-3053) C:/altera/13.1/FlipFlopsProjects/flipflop.v(30): Illegal output or inout port connection for "port 'Q'".
Any ideas or thoughts?
错误在于顶层模块的输入声明......它们需要是电线,而不是寄存器
在顶层模块中,Q需要是regs,D需要是wire。
The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:yoyou2525@163.com.