SystemVerilog: Parameter used in concatenation gives error with irun

Question

Cadence irun gives error for below code, where fifo_depth_base2 is parameter as below:

ncvlog: *E,NONOWD (buff_mgr.v,17|46): Illegal use of a constant without an explicit width specification [4.1.14(IEEE)].

I can understand this error, but my question is how would I otherwise assign it for parameterized design.

// rd pointer and read logic
always @(posedge clk or posedge rst) begin
    if(rst) rd_ptr <= 0;
else begin  
    case({flush, rd})
        2'b10, 2'b11: rd_ptr <= {fifo_depth_base2{'b0}}; // error here
        ...
 endcase
end
end

Answer 1

You are missing a 1 before 'b0 . The simulator doesn't know the bit size of 'b0 because it is not specified.

{fifo_depth_base2{'b0}}; should be {fifo_depth_base2{ 'b0}}; 'b0}};

With SystemVerilog you can use: rd_ptr <= '0; , where '0 means fill zeros