GCC ARM register expected

Question

I'm trying to port bunny to armv7h, which uses some x86 asm stuff that I'm having trouble converting to asm.

static __inline__ void atomic_inc(volatile int* ptr){
    __asm__ __volatile__("lock incl %0": "=m" (*ptr): "m" (*ptr));
}    

static __inline__ void atomic_dec(volatile int* ptr){
    __asm__ __volatile__("lock decl %0": "=m" (*ptr): "m" (*ptr));
}

Is what's there, I've tried

"ADD/SUB %0 %0": "=r" (*ptr): "m" (*ptr));

And both give

Error: ARM register expected -- `add [r3] [r3]'

and

Error: ARM register expected -- `sub [r4] [r4]'

Compiled using:

armv7l-unknown-linux-gnueabihf-gcc -Wall -O3 -funroll-loops -fno-strict-aliasing
-ffast-math -Wno-pointer-sign -mcpu=cortex-a15 -mfpu=neon -marm

Answer 1

The clue lies in the error message - which is entirely accurate.

ARM arithmetic instructions take three operands :

ADD{S} rd, rs, <operand>

SUB{S} rd, rs, <operand>

Where operand is one of:

• A register
• An immediate value
• A register shifted by a constant
• A register shifted by another register

in your case, I imagine you would want an immediate constant of 1 , which would give an assembler instruction of

ADD rd, rd, #1

However, this misses the fundamental flaw that you are trying to implement an atomic increment of a memory location . The compiler is generating a load from memory instruction in order to implement the dereference of ptr . It's not immediately obvious it ever generates a stores of the result. Even if it did, this would be at best, a non-atomic sequence of 3 instructions (load, increment, store).

I would recommend looking at GCC's atomic intrinsics rather than rolling your own.