ARM Cortex M3: Atomic Writes

Question

I'm developing a shared data library on a ARM Cortex-M3 architecture (LPC1769) and I'm wondering if I need mutexes or locking around the writes.

Is a 32 bit float read/write atomic?

-- EDIT -- I added the disassembly for a write function for a uint32_t and a float:

00000000 <setSharedDataUint>:
   0:   b480        push    {r7}
   2:   b083        sub sp, #12
   4:   af00        add r7, sp, #0
   6:   4603        mov r3, r0
   8:   6039        str r1, [r7, #0]
   a:   71fb        strb    r3, [r7, #7]
   c:   79fb        ldrb    r3, [r7, #7]
   e:   4a05        ldr r2, [pc, #20]   ; (24 <setSharedDataUint+0x24>)
  10:   00db        lsls    r3, r3, #3
  12:   4413        add r3, r2
  14:   683a        ldr r2, [r7, #0]
  16:   605a        str r2, [r3, #4]
  18:   370c        adds    r7, #12
  1a:   46bd        mov sp, r7
  1c:   f85d 7b04   ldr.w   r7, [sp], #4
  20:   4770        bx  lr
  22:   bf00        nop
  24:   00000000    .word   0x00000000
            24: R_ARM_ABS32 .bss.dataArray

 00000000 <setSharedDataFloat>:
   0:   b480        push    {r7}
   2:   b083        sub sp, #12
   4:   af00        add r7, sp, #0
   6:   4603        mov r3, r0
   8:   6039        str r1, [r7, #0]
   a:   71fb        strb    r3, [r7, #7]
   c:   79fb        ldrb    r3, [r7, #7]
   e:   4a05        ldr r2, [pc, #20]   ; (24 <setSharedDataFloat+0x24>)
  10:   00db        lsls    r3, r3, #3
  12:   4413        add r3, r2
  14:   683a        ldr r2, [r7, #0]
  16:   605a        str r2, [r3, #4]
  18:   370c        adds    r7, #12
  1a:   46bd        mov sp, r7
  1c:   f85d 7b04   ldr.w   r7, [sp], #4
  20:   4770        bx  lr
  22:   bf00        nop
  24:   00000000    .word   0x00000000
            24: R_ARM_ABS32 .bss.dataArray

They look identical which makes me assume that the 32-bit float write is also atomic

Answer 1

See the Architecture Reference Manual for the specifics: In short, any aligned 32-bit memory access is atomic in the sense that the result is either all 4 bytes of the old value, or all 4 bytes of the new value, and never some mix of the two. Unaligned accesses do not have this guarantee.

That's for pure reads or writes - for any kind of read-modify-write sequence, you need a load/store-exclusive loop to make the sequence of instructions appear atomic. Similarly if the shared data pointer is liable to change under your feet between reading it and reading/writing the actual value to the location it points at, you will need to wrap the whole operation in an exclusive sequence for safety.

Answer 2

The cortex M3 natively supports 32 bit operations so, when working with a 32 bit data type, the operations should be performed in one instruction; which means it's atomical.

if you were to try the same with 64bit data types, which have to be emulated (usually a struct containing 32bit high part and 32 bit low part) you should see multiple instructions being performed for that operation.