Error loading design ModelSim 10.1

Question

I'm trying to create a counter using D flip-flop asynchronous resets. It compiles successfully but this is the error I got during the simulation in ModelSim:

'error loading design'

And above it, I found four other errors:

# ** Error: (vopt-3053) C:/modeltech64_10.1c/examples/project3.v(48): Illegal output port connection for "'q' (1st connection)".
# 
# ** Error: (vopt-3053) C:/modeltech64_10.1c/examples/project3.v(49): Illegal output port connection for "'q' (1st connection)".
# 
# ** Error: (vopt-3053) C:/modeltech64_10.1c/examples/project3.v(50): Illegal output port connection for "'q' (1st connection)".
# 
# ** Error: (vopt-3053) C:/modeltech64_10.1c/examples/project3.v(51): Illegal output port connection for "'q' (1st connection)".

This is the program:

module Flipflap_TN(q,t,clk,reset);
input t,clk,reset;
output q;
reg q;
reg temp=0;

always@(negedge clk,negedge reset)
begin
  if(reset)
   begin
   if(t==0)
     temp=temp;
   else
     temp=~temp;
     q=temp;
   end
  else
   q=0;
  end

 endmodule


module counter(q,t,clk,m,reset);
input t,clk,m,reset;
output [3:0]q;
reg [3:0]q;

wire h0,h1,h2,h3;
xor(h0,clk,m);
xor(h1,q[0],m);
xor(h2,q[1],m);
xor(h3,q[2],m);

Flipflap_TN FTN1(q[0],t,h0,reset);
Flipflap_TN FTN2(q[1],t,h1,reset);
Flipflap_TN FTN3(q[2],t,h2,reset);
Flipflap_TN FTN4(q[3],t,h3,reset);

initial
begin
 if(m==1 & q==4'b1111)
   q=4'b0;
 else if(m==0 & q==4'b1010)
   q=4'b0;
end

endmodule

How to fix these errors?

Answer 1

The output of a module must drive a wire not a reg . You should not be assigning q within counter .

In Flipflap_TN , sequential logic should use non-blocking assignments ( <= ), not blocking ( = )

Daisy-chain counters (where the q of one flop is a function of the clock of another flop) are not recommended for real designs. They have bad timing and can have glitchy outputs. It is fine for learning but best if all the flops are driven by the exact same clock.