MSP430 microcontroller - how to check addressing modes

Question

I'm programming a MSP430 in C language as a simulation of real microcontroller. I got stuck in addressing modes ( https://en.wikipedia.org/wiki/TI_MSP430#MSP430_CPU ), especially:

• Addressing modes using R0 (PC)

• Addressing modes using R2 (SR) and R3 (CG), special-case decoding

  1. I don't understand what does mean 0(PC), 2(SR) and 3(CG). What they are?
  2. How to check these values?

Answer 1

so for the source if the as bits are 01 and the source register bits are a 0 which is the pc for reference then

ADDR Symbolic. Equivalent to x(PC). The operand is in memory at address PC+x.

if the ad bit is a 1 and the destination is a 0 then also

ADDR Symbolic. Equivalent to x(PC). The operand is in memory at address PC+x.

x is going to be another word that follows this instruction so the cpu will fetch the next word, add it to the pc and that is the source

if the as bits are 11 and the source is register 0, the source is an immediate value which is in the next word after the instruction.

if the as bits are 01 and the source is a 2 which happens to be the SR register for reference then the address is x the next word after the instruction (&ADDR)

if the ad bit is a 1 and the destination register is a 2 then it is also an &ADDR

if the as bits are 10 the source bits are a 2, then the source is the constant value 4 and we dont have to burn a word in flash after the instruction for that 4.

it doesnt make sense to have a destination be a constant 4 so that isnt a real combination.

repeat for the rest of the table.

you can have both of these addressing modes at the same time

mov #0x5A80,&0x0120

generates

c000:   b2 40 80 5a     mov #23168, &0x0120 ;#0x5a80
c004:   20 01

which is

0x40b2 0x5a80 0x0120

0100000010110010
0100 opcode mov
0000 source
1 ad
0 b/w
11 as
0010 destination

so we have an as of 11 with source of 0 the immediate #x, an ad of 1 with a destination 2 so the destination is &ADDR. this is an important experiment because when you have 2 x values, a three word instruction basically which one goes with the source and which the destination

0x40b2 0x5a80 0x0120

so the address 0x5a80 which is the destination is the first x to follow the instruction then the source 0x0120 an immediate comes after that.

if it were just an immediate and a register then

c006:   31 40 ff 03     mov #1023,  r1  ;#0x03ff

0x4031 0x03FF

0100000000110001
0100 mov
0000 source
0 ad
0 b/w
11 as
0001 dest

as of 11 and source of 0 is #immediate the X is 0x03FF in this case the word that follows. the destination is ad of 0

Register direct. The operand is the contents of Rn 

where destination in this case is r1

so the first group Rn, x(Rn), @Rn and @Rn+ are the normal cases, the ones below that that you are asking about are special cases, if you get a combination that fits into a special case then you do that otherwise you do the normal case like the mov immediate to r1 example above. the destination of r1 was a normal Rn case.

Answer 2

• As=01, Ad=1, R0 ( ADDR ): This is exactly the same as x(Rn) , ie, the operand is in memory at address R0+x.

  This is used for data that is stored near the code that uses it, when the compiler does not know at which absolute address the code will be located, but it knows that the data is, eg, twenty words behind the instruction.

• As=11, R0 ( #x ): This is exactly the same as @R0+ , and is used for instructions that need a word of data from the instruction stream. For example, this assembler instruction:

   MOV #1234, R5 

  is actually encoded and implemented as:

   MOV @PC+, R5 .dw 1234 

  After the CPU has read the MOV instruction word, PC points to the data word. When reading the first MOV operand, the CPU reads the data word, and increments PC again.

• As=01, Ad=1, R2 ( &ADDR ): this is exactly the same as x(Rn), but the R2 register reads as zero, so what you end up with is the value of x.

  Using the always-zero register allows to encode absolute addresses without needing a special addressing mode for this (just a special register).

• constants -1/0/1/2/4/8: it would not make sense to use the SR and CG registers with most addressing modes, so these encodings are used to generate special values without a separate data word, to save space:

   encoding: what actually happens: MOV @SR, R5 MOV #4, R5 MOV @SR+, R5 MOV #8, R5 MOV CG, R5 MOV #0, R5 MOV x(CG), R5 MOV #1, R5 (no word for x) MOV @CG, R5 MOV #2, R5 MOV @CG+, R5 MOV #-1, R5