Cortex-m0+ psr, iepsr, iapsr, and eapsr registers

Question

In the cortex-m0+ processor, there is a register called the "program status register" (psr for short) that holds 3 important pieces of information:

• The condition flags (zero, carry, etc...), in bits <31:28>
• The exception number, in bits <5:0> (tells you which interrupt is being serviced, == 0 for no interrupt)
• The "Am I in thumb mode" flag, in bit <24>.

As you'd expect, all of these bit fields can be accessed by just reading the psr with an mrs r0, psr instruction. The thing I'm confused about is on page 16-17 of the m0+ User Manual . The manual tells me that I can access, say, ONLY the exception number bits (with all other bits set to zero), by reading the "ipsr" instead of the "psr". Essentially,

    mrs r0, ipsr

and

    mrs r0, psr
    and r0, r0, #0x3f

are identical.

Why are these alternate methods of accessing bitfields in the psr offered?

My best guess is that context-switching or ISR code would want to read ONLY the bottom 6 bits, and this saves a (not very expensive, imo) bitmasking operation.

Answer 1

What I think you're missing is that the mrs / msr instructions have been around since ARMv 3 well over 20 years ago (when the PC grew from 24 to 32 bits so the other stuff got kicked out of r15 into a special status register). The ARM encodings have always had to differentiate between SPSR vs. CPSR vs. parts of CPSR. When Thumb-2 came along after ARMv6, the Thumb encodings thus also had to differentiate between SPSR vs. CPSR vs. parts of CPSR on ARM1156/Cortex-A.

The point is, then, that there are already bits in those encodings to encode more than one target status register in the classic/A-class architectures - as it happens, there are still a fair few reserved bits spare even after the ARMv7-A virtualisation extensions also added various banked registers to the mix. Now imagine you're designing a new architecture to push your successful embedded ISA/design expertise/development ecosystem into the lower-end microcontroller space, where 8-bit parts dominate and code size and efficiency is critical . The question then becomes why would you not press those otherwise-unused instruction encoding bits into action to make status register accesses as efficient as they possibly can be?

Answer 2

If you only need the IPSR field, you can just use the corresponding (single) instruction.

I think that the second example is just to clarify the behaviour, as this is the CPU which is responsible for masking the data and set all the top bits to 0.