How to add clock in Xilinx/Verilog

Question

I am new in Xilinx. Here's my code,and i want to add clock in it. Please tell me how to add clock. Thanks

code

module Traffic(
    output reg red1,
    output reg red2,
    output reg red3,
    output reg red4,
    output reg yel1,
    output reg yel2,
    output reg yel3,
    output reg yel4,
    output reg gr1,
    output reg gr2,
    output reg gr3,
    output reg gr4,
    input [1:0] c1,
     input [1:0] c2
    );

always @(c1,c2,red1,red2,red3,red4,yel1,yel2,yel3,yel4,gr1,gr2,gr3,gr4)
begin

case({c1,c2}) 
4'b0000:begin red1=0;red2=1;red3=1;red4=0;  yel1=1;yel2=0;yel3=0;yel4=1;  gr1=0;gr2=0;gr3=0;gr4=0; end
4'b0001:begin red1=1;red2=1;red3=1;red4=0;  yel1=0;yel2=0;yel3=0;yel4=0;  gr1=0;gr2=0;gr3=0;gr4=1; end

4'b0010:begin red1=0;red2=1;red3=1;red4=0;  yel1=1;yel2=1;yel3=0;yel4=0;  gr1=0;gr2=0;gr3=0;gr4=0; end
4'b0011:begin red1=1;red2=1;red3=1;red4=1;  yel1=0;yel2=0;yel3=0;yel4=0;  gr1=0;gr2=1;gr3=0;gr4=0; end

4'b0100:begin red1=1;red2=0;red3=0;red4=1;  yel1=0;yel2=1;yel3=1;yel4=0;  gr1=0;gr2=0;gr3=0;gr4=0; end
4'b0101:begin red1=1;red2=1;red3=0;red4=1;  yel1=0;yel2=0;yel3=0;yel4=0;  gr1=0;gr2=0;gr3=1;gr4=0; end

4'b0110:begin red1=1;red2=1;red3=0;red4=0;  yel1=0;yel2=0;yel3=1;yel4=1;  gr1=0;gr2=0;gr3=0;gr4=0; end
4'b0111:begin red1=1;red2=1;red3=1;red4=0;  yel1=0;yel2=0;yel3=0;yel4=0;  gr1=0;gr2=0;gr3=0;gr4=1; end

endcase
end
endmodule
-------------
Text Fixture
-------------
module tf;

    // Inputs
    reg [1:0] c1;
    reg [1:0] c2;

    // Outputs
    wire red1;
    wire red2;
    wire red3;
    wire red4;
    wire yel1;
    wire yel2;
    wire yel3;
    wire yel4;
    wire gr1;
    wire gr2;
    wire gr3;
    wire gr4;

    // Instantiate the Unit Under Test (UUT)
    Traffic uut (
        .red1(red1), 
        .red2(red2), 
        .red3(red3), 
        .red4(red4), 
        .yel1(yel1), 
        .yel2(yel2), 
        .yel3(yel3), 
        .yel4(yel4), 
        .gr1(gr1), 
        .gr2(gr2), 
        .gr3(gr3), 
        .gr4(gr4), 
        .c1(c1), 
        .c2(c2)
    );

    initial begin
        c1 = 2'b00;c2 = 2'b00;
        #100 c1 = 2'b00;c2 = 2'b01;
        #100 c1 = 2'b00;c2 = 2'b10;
        #100 c1 = 2'b00;c2 = 2'b11;
        #100 c1 = 2'b01;c2 = 2'b00;
        #100 c1 = 2'b01;c2 = 2'b01;
        #100 c1 = 2'b01;c2 = 2'b10;
        #100 c1 = 2'b01;c2 = 2'b11;
    end

Answer 1

If I understand your question correctly, you would like the outputs of your module to be synchronous to a clock. you need to declare the clock as in input wire , and alter the always block to use the posedge clk . It's also good to add a reset -- you can have a synchronous reset or an asynchronous reset. Here's how such a block would be structured, with an asynchronous reset:

module Traffic(
    input wire clk,
    input wire resetb, // negative edge asynchronous reset
    output reg red1,
    output reg red2,
    output reg red3,
    output reg red4,
    output reg yel1,
    output reg yel2,
    output reg yel3,
    output reg yel4,
    output reg gr1,
    output reg gr2,
    output reg gr3,
    output reg gr4,
    input [1:0] c1,
     input [1:0] c2
    );

always @(posedge clk or negedge resetb)
begin
    if (!resetb) begin
        red1 <= 'd0;
        // etc....
    end else begin
        case({c1,c2}) 
            4'b0000:begin 
                red1<=0;red2<=1;red3<=1;red4<=0;  
                yel1<=1;yel2<=0;yel3<=0;yel4<=1;  
                gr1<=0;gr2<=0;gr3<=0;gr4<=0; 
            end
            4'b0001:begin 
                red1<=1;red2<=1;red3<=1;red4<=0;  
                yel1<=0;yel2<=0;yel3<=0;yel4<=0;  
                gr1<=0;gr2<=0;gr3<=0;gr4<=1; 
            end

            // etc...

        endcase
    end
end
endmodule