Specifying input sources (instead of intermediates) as prerequisites to target in Makefile

Question

After reading the first few chapters of Managing Projects with GNU Make , I've come up with my first non-trivial Makefile

all: libTest.a

libTest.a : Test.o MWE.o Test.dlink.o MWE.dlink.o
    nvcc -ccbin g++ -m64 -gencode arch=compute_30,code=sm_30 -lib -o $@ $^

%.a : %.dlink.o %.o
    nvcc -ccbin g++ -m64 -gencode arch=compute_30,code=sm_30 -lib -o $@ $^

%.dlink.o : %.o
    nvcc -ccbin g++ -m64 -gencode arch=compute_30,code=sm_30 -dlink -o $@ $<

%.o: %.cu
    nvcc -ccbin g++ -m64 -gencode arch=compute_30,code=sm_30 -dc -o $@ -c $<

clean:
    rm -f *.o *.dlink.o

This Makefile works but I really don't like specifying the intermediate files Test.o MWE.o Test.dlink.o MWE.dlink.o as prerequisites to libTest . I'd rather specify the input files Test.cu and MWE.cu or better still the wildcard %.u .

Answer 1

As long as you can prepare a command (or set of commands) to build libTest.a from Test.cu and MWE.cu , you can have just a rule:

libTest.a: Test.cu MWE.cu
    list
    of
    commands
    needed
    to
    build
    the
    library

but this is hardly a reasonable way of using make . What you have shown us in original question is a make -ish way of doing things. However if that's your whole Makefile the rule %.a : %.dlink.o %.o is superfluous here.

What you can do is to generate those prerequisites automatically:

SOURCES=Test.cu MWE.cu
libTest.a: $(SOURCES:%.cu=%.o) $(SOURCES:%.cu=%.dlink.o)
    nvcc -ccbin g++ -m64 -gencode arch=compute_30,code=sm_30 -lib -o $@ $^

If you prefer to not add filenames manually to SOURCES but prefer to use all *.cu files available in current directory, replace the SOURCES assignment with:

SOURCES=$(wildcard *.cu)