How to give a delay of 1 clock cycle in a combinational block verilog

Question

I have a combinational code that I have, In that code I would like to turn off a signal after 1 clock cycle, ie initially it is 1, and after one clock cycle it should be 0. Is there any way I can do it and if possible it should be able to synthesize on an FPGA. The code is as follows:

always@(ao or bo or co or dod or eo or fo or go or ho)
    begin
    temp_out = {ho,go,fo,eo,dod,co,bo,ao};
    out_flag = 1;
    //after one clock cycle it should go to 0 ;
    //help is required over here
    out_flag = 0;
    end

Answer 1

You cannot do it in a pure combinational synthesizable manner. You need a flop (which is synthesizable) and a reset to set the signal to a know value, say to 0. So, you can delay 1 clock cycle after reset as the following:

always @(posedge clk) begin 
    if (reset)
        out_flag <= 0;
    else 
        out_flag <= 1;
end

you need to figure out exact timing and use correct number of flops for you particular situation. You might want to have an asynchronous reset versus synchronous as in the above example.