Verilog test bench for loop(priority, problem with value)

Question

For i=0 and j=0 this code makes my a,b,cin and s signals to be xxxxxxxx .

For i=0 and j=1 my a,b,cin and s are all 00000000 .Which should be the result for my adder for i=0 j=0 cin =0. Whats wrong? I am sure my adder module is correct.

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Most of the trouble came at first with the for loops and began when some of the values werent printed and then after i added begin end in each loop i saw the full loop result whith the above problem^^^^^.Still dont know how it worked but it did

module test_cla4_n;

    reg [7:0] a,b;
    reg cin;

    wire [7:0] s;
    wire cout;

    integer i;
    integer j;
    integer cv;

    cla4_n#(.n(8)) UUT
        (.a(a), .b(b),
              .cin(cin),
             .s(s), .cout(cout));

    initial 
     begin
    for(cv=0;cv<=1;cv=cv+1)
     begin
        for (i=0;i<6;i=i+1) 
         begin
            for (j=0;j<6;j=j+1)
             begin
                #100 a = j; b = i; cin = cv;

             end
         end
     end

     end

    initial
     begin
    $monitor($time,   ,"a=%9b, b=%9b, cin=%b, sum=%9b", a, b, cin, s); 
     end
    endmodule

Answer 1

Whether you put the #100 delay before or after the assignments does not matter as long as you understand how the delay works wrt the loop.

The only place begin / end is required anywhere in the code you show is with the innermost for(j=0; ` loop.

Answer 2

All 4-state variables and nets in verilog are initialized with 'x'. Therefore, before you drive something in your simulation, all signals will remain 'x'.

In your test bench you use #100 delay in your loop. In your expression it means that all the assignments which follow #100 will happen only after 100 verilog simulation cycles (or whatever you set with 'timescale'). But before it all your values will remain 'x'.

Now when #100 triggers in you will have the following:

    #100 
    a = j; <-- 0
    b = i; <-- 0
    cin = cv; <-- 0
    j = j + 1; <-- 1 << from the loop

You end up with a = 0, b = 0, c = 0, and j will change to '1'.

Now your simulation will kick in and calculate the results for the above. You can continue this train of thoughts for the rest of simulation.

In order for all those statement to happen in side the loop after #100, yes you need to put begin/end around them. Otherwise only the first statement will be evaluated in the innermost loop. This is similar to any programming language.

for (j=0;j<6;j=j+1)
begin
  #100 // wait here for 100 simulation ticks
    a = j; 
    b = i; 
    cin = cv;
end