posedge or negedge in the body of the loop

Question

I have following verilog code. I can't find answer what is the effect of using posedge in the middle of the loop or after a <= x;b<=ri . I think that always begin gets executed always and after that the function will be blocked on posedge clk (after the integer d line). When the clock will rise the next line will be executed.(namely r <= 0 ).

If this is true then the next posedge clk (after <= x ; b <= ri and c = ri ) will be executed on the same clock edge or the require another clock edge and what is the reason of using posedge in the middle of code instead of in beginning?

always
begin :two
   real c;
   integer d;
   @(posedge clk)
      r <= 0;
   if (k) 
   begin
      a <= x; b <= ri;
      @(posedge clk);
      begin :loop
      forever
      begin
         c = ri;
         @(posedge clk);
         d = $rtoi(c*4);
         if (abs(b-c) > abs(a-b)) disable loop;
         r <= $rtoi(j*4);
      end
   end 
   d = 3*d; k <= 1’b0; r <= d + 1;
end

Answer 1

then the next posedge clk (after <= x ; b <= ri and c = ri) will be executed on the same clock edge

No, every @(posedge clk); will block execution until the rising edge is seen and it will continue after that.

what is the reason of using posedge in the middle of code instead of in beginning?

I don't know why the code was written that way, for that I would have to know (or guess) which problem the author was trying to solve.

As mentioned above: a @(posedge clk); will block execution until the rising edge is seen. So you should read the code as a particular sequence of events:

1. wait for a rising clock edge then set r to zero.

2. if k set a , b and again wait for a rising clock edge.

3. set c (For some reason this is a blocking assignment) and again wait for a rising clock edge.

   etc.