AVR Assembly why does LDI instruction can only use R16 - R31 registers

Question

Hello I came across this exam question in a past paper and I am baffled, so far no research has given me a conclusive answer as most people just say its a limitation of the processor. I am very sure we did not cover this in class.

Does anyone know why?

Answer 1

The simple answer is that LDI is just supported for the upper 16 registers.

When you have a look at the ISA (instruction set architecture) you'll notice that the same applies to SUBI , SBCI , ANDI , ORI and CPI , each of which needs 12 bits in the opcode table: 8 bits for the 8-bit immediate and 4 bits to encode which of R16... R31 is the destination. This means that just to provide these 6 instructions with immediate, you are already occupying 37.5% of opcodes.

Supporting R0... R31 would require 75% of opcode just for 6 instructions: All AVR opcodes are 16-bit opcodes (except LDS , STS , CALL , JMP which are 32 bit), and you can only encode so much instructions with 16 bits

Take for example the following 2-reg instructions: ADD , ADC , SUB , SBC , CP , CPC , AND , OR , EOR , LSR , ASR , ROR , MOV . Each of these 13 instructions occupies 2^(5+5) opcodes because each one has to encode one of 2^5 possible source resp destination registers, summing up to more than 20% of opcode space. And we did not yet consider jumps ( RJMP , RCALL , branches) or memory accesses like LDD , STD , IN , OUT .

Terminology: "opcode" above means all the bits needed to encode one specific machine instruction.