MakeFile: Implicit file declaration warnings in C

Question

i am new to creating Make File and im running into some error caused by dependencies, basically in each "*.c" file i only include it self for example: Main will only include Main.h. As a result of this, i am trying to create the dependencies on MakeFile, the dependencies are:

-Main.c uses functions/structs that are declared in memory.h, synchronization.h, client.h, server.h proxy.h and process.h

-memory.c uses functions/structs that are declared in synchronization.h

-process.c uses functions/structs that are declared in client.h, proxy.h and server.h

Some other dependencies are made by #include in the header files.

Some of the errors i have got so far are:

gcc -c process.c
process.c: In function ‘launch_process’:
process.c:25:46: warning: implicit declaration of function ‘execute_client’ [-Wimplicit-function-declaration]
             data->client_stats[process_id] = execute_client(process_id, buffers, data, sems);

process.c:30:45: warning: implicit declaration of function ‘execute_proxy’ [-Wimplicit-function-declaration]
             data->proxy_stats[process_id] = execute_proxy(process_id, buffers, data, sems);

process.c:33:46: warning: implicit declaration of function ‘execute_server’ [-Wimplicit-function-declaration]
             data->server_stats[process_id] = execute_server(process_id, buffers, data, sems);

gcc -c main.c
main.c: In function ‘launch_processes’:
main.c:159:32: warning: implicit declaration of function ‘launch_process’; did you mean ‘launch_processes’? [-Wimplicit-function-declaration]
         data->client_pids[i] = launch_process(i, 0, buffers, data, sems);

main.c: In function ‘wait_processes’:
main.c:243:33: warning: implicit declaration of function ‘wait_process’; did you mean ‘wait_processes’? [-Wimplicit-function-declaration]
         data->client_stats[i] = wait_process(data->client_pids[i]); //o retorno dos processos client_pids etc ira returnar o return do execute_client sendo que sera o "exit" do processo

PS:I am not allowed to change header files and sorry for the long question by have spent more then 24 hours straight around this and this is not allowing me to test my finished project, Thank you.

Here is the makefile that i have created.

sovaccines: client.o proxy.o server.o process.o main.o memory.o  synchronization.o 
            gcc client.o proxy.o server.o process.o main.o memory.o  synchronization.o  -o sovaccines -lrt -pthread -g

main.o: main.c ../include/memory.h ../include/synchronization.h ../include/client.h ../include/proxy.h ../include/server.h ../include/process.h
            gcc -c main.c

client.o: client.c
            gcc -c client.c

memory.o: memory.c ../include/synchronization.h
            gcc -c memory.c 

process.o: process.c ../include/client.h ../include/proxy.h ../include/server.h
            gcc -c process.c

proxy.o: proxy.c
            gcc -c proxy.c

server.o: server.c
            gcc -c server.c

synchronization.o: synchronization.c 
            gcc -c synchronization.c 

Answer 1

Your warnings simply tell you that you forgot to include the correct header files in your C source files, or that you did not tell the compiler where to find these header files. Example: if in main.c you have something like:

#include "memory.h"
#include "synchronization.h"
#include "client.h"
#include "server.h"
#include "proxy.h"
#include "process.h"

you should pass the -I../include option to gcc . As you are using GNU make your Makefile could then look like this:

SRC     := $(wildcard *.c)
OBJ     := $(patsubst %.c,%.o,$(SRC))
INCLUDE := ../include
CFLAGS  := -g -I$(INCLUDE)
LDLIBS  := -lrt -pthread
VPATH   := $(INCLUDE)

sovaccines: $(OBJ)
    $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LDLIBS)

main.o: memory.h synchronization.h client.h proxy.h server.h process.h
memory.o: synchronization.h
process.o: client.h proxy.h server.h

%.o: %.c
    $(CC) -c $(CFLAGS) $< -o $@

• wildcard and patsubst are make functions
• CC , CFLAGS , LDLIBS ... are Variables Used by Implicit Rules
• VPATH defines a Search Path for All Prerequisites
• $@ , $^ , $< ... are Automatic Variables
• %.o: %.c is a Pattern Rule

Note that there are ways to automatically generate the dependencies of source files on header files. If you are interested, have a look, for example, at this excellent guide: Auto-Dependency Generation .

Note also that make knows already how to compile and link C projects. It has Implicit Rules . This is another way to further simplify your Makefile. In the proposed Makefile above you could, for instance, omit the pattern rule completely and also the recipe of the sovaccines: $(OBJ) rule.