Master-slave J-K flip-flop has no output

Question

I have written the testbench code and design code for Master-slave JK flip flop, but output ain't coming. Please point out the error.

Test bench.sv

module JK_ff_tb;
 
reg clk;
reg reset;
reg j,k;
 
wire q;
wire qb;
 
jk_flip_flop_master_slave jkflipflop( .clk(clk), .reset(reset), .j(j), .k(k), .q(q), .q_bar(qb) );
 
initial begin
  $dumpfile("dump.vcd"); $dumpvars;
$monitor(clk,j,k,q,qb,reset);
 
j = 1'b0;
k = 1'b0;
reset = 1;
clk=1;
 
#10
reset=0;
j=1'b1;
k=1'b0;
 
#100
reset=0;
j=1'b0;
k=1'b1;
 
#100
reset=0;
j=1'b1;
k=1'b1;
 
#100
reset=0;
j=1'b0;
k=1'b0;
 
#100
reset=1;
j=1'b1;
k=1'b0;
 
end
always #25 clk <= ~clk;
 
endmodule

Design.sv

// Code your design here
module jk_flip_flop_master_slave(j,k,clk,reset,q,q_bar);
input j,k,clk,reset;
output q,q_bar;
 

reg q,q_bar; // Active low reset signal.
   
   wire   MQ;  // The master's Q output.
   wire   MQn; // The master's Qn output.
   wire   Cn;  // The clock input to the slave shall be the                   complement of the master's.
   wire   J1;  
   wire   K1;  
   wire   J2;  // The actual input to the first SR latch (S).
   wire   K2;  // The actual input to the first SR latch (R).

   assign J2 = !reset ? 0 : J1;  // Upon reset force J2 = 0
   assign K2 = !reset ? 1 : K1;  // Upon reset force K2 = 1
   
  and(J1, j, q_bar);
  and(K1, k, q);   
  not(Cn, clk);   
  sr_latch_gated master(MQ, MQn, clk, J2, K2);
  sr_latch_gated slave(q, q_bar, Cn, MQ, MQn);   
endmodule // jk_flip_flop_master_slave

Sr_Latched flip flop module

module sr_latch_gated(Q, Qn, G, S, R);
   output Q;
   output Qn;
   input  G;   
   input  S;
   input  R;
   
   wire   S1;
   wire   R1;
   
   and(S1, G, S);
   and(R1, G, R);   
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
endmodule // sr_latch_gated

I have coded the entire thing in EDA-playground.

The diagram generated was really abrupt as well. If there is another logic that can be implemented easily, do tell.

Answer 1

I get compile errors on 2 different simulators. You should not declare q and q_bar as reg in the jk_flip_flop_master_slave module. You should delete this line:

reg q,q_bar; // Active low reset signal.

Then it compiles and simulates for me. I see this output:

100xx1
110xx0
010010
110010
010010
110010
101010
001010
101010
001010
...