Systemverilog expansion rule

Question

When I review some codes, I found something strange.
It seems that it comes from expansion and operation priority.
(I know that because "sig" is declared with 'signed', $signed is not necessary and '-sig' is correct one, anyway..)

reg signed [9:0] sig;
reg signed [11:0] out;

initial
begin
    $monitor ("%0t] sig=%0d, out=%0h", $time, sig, out);
    sig = 64;
    out = $signed(-sig);
#1
    out = -$signed(sig);
#1
    sig = -512;
    out = $signed(-sig);
#1
    out = -$signed(sig);
#1
$finish;
end

Simulation result for above codes is,

0] sig=64, out=-64
2] sig=-512, out=-512
3] sig=-512, out=512

When sig=-512, I expected that 10 bits sig would be expanded to 12bits before negation, but it was expanded after negation.
Therefore negation of -512 was still -512, and after expansion, it had a -512.
I guess "$signed() blocks expansion..Any idea what happens??

Answer 1

First pf all,

-512 and 512 are identical numbers in 10-bit represenntation. It actually can only hold signed values from -512 to 511.

Secondly, unary operator '-' returns an unsigned value. Therefore, no sign extension happens. You can try the following to verify:

 out = $signed(-$signed(sig));