Here is the L3 cache (shared) configuration on my Intel Xeon Silver 4210R CPU-
$ getconf -a | grep LEVEL3_CACHE
LEVEL3_CACHE_SIZE 14417920
LEVEL3_CACHE_ASSOC 11
LEVEL3_CACHE_LINESIZE 64
This configuration implies that the number of sets in the cache is-
Now I am trying to understand the addressing of the cache .
Here, the cache line (or the block) size is 64 bytes and intel uses the byte-addressable system. Therefore, the least significant bits of cache address should be used for block offset.
With a similar calculation, the number of address bits that should be used for set indexing is , but this fraction value confuses me.
Am I missing something? How many bits are exactly used here for set indexing?
Am I missing something?
This processor has 10 cores — your formula doesn't account for # of cores, so if you divide by 10 it is an even multiple of 2.
How many bits are exactly used here for set indexing?
11 bits, I believe
L3$ 13.75 MiB 10x1.375 MiB 11-way set associative write-back
read more here: https://en.wikichip.org/wiki/intel/xeon_silver/4210r
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