Benchmarking on CMSIS RTOS Cortex M-33

Question

I'm trying to time the duration of a function on a Cortex M33 with CMSIS RTOS. I'm currently reading cycles directly from the ARM_CM_DWT_CYCCNT register.

This is working, but I'm wondering whether I can do anything else to increase the precision/variance of my measurement? Ie limit interrupts etc.?

Some third party code has included the use of int_lock() and int_unlock(lock) but I can't find any CMSIS RTOS documentation of this usage.

Answer 1

Your "third-pary" routines are most likely some sort of wrapper around a CPSR manipulation. Intuitively I'd expect to wrap the code section in something like:

lock_handle = int_lock() ; 
... 
int_unlock( lock_handle );

But unless you have documentation or access to the source of these functions to be certain how they behave, you might do well to avoid using them.

CMSIS RTOS does not provide facilities to disable interrupts or implement critical sections. In general you have failed in your design if your application needs critical-sections. More generally however CMSIS CORE (CMSIS is more than just CMSIS RTOS) has the NVIC API with NVIC_DisableIRQ() and NVIC_EnableIRQ() functions to enable/disable individual interrupts (in case some such as SYSTICK are essential to your benchmark).

Means to globally disable all interrupts is part of CMSIS Core Register Access which defines __disable_irq() and __enable_irq() .

It is likely that the third-party enable/disable functions provide a handle to ensure that enabling and disabling are correctly paired or perhaps a nest counter so that only the outer enable of a nested disable re-enables interrupts. These are all mechanisms that are trivial to implement using the available the CMSIS primitives, but may not be needed in your case.