How to no separate into Output and Input when using AUTOINST with verilog-mode

Question

For InstModule like this

        module InstModule (
           input i1,
           output [31:0] o1,
           input i2,
           output [31:0] o2);
        endmodule

verilog-mode will expand it

           InstModule instName
             (/*AUTOINST*/);

into this

           InstModule instName
             (/*AUTOINST*/
          // Outputs
          .o1           (o1[31:0]),
          .o2           (o2[31:0]),
          // Inputs
          .i1           (i1),
          .i2           (i2));

However, I hope it can be like this. Just like declaration order and not separate into two groups.

           InstModule instName
             (/*AUTOINST*/
          .i1           (i1),
          .o1           (o1[31:0]),
          .i2           (i2),
          .o2           (o2[31:0]));

Is there a setting of verilog-mode I can rely on?

or is there a way I can modify verilog-mode.el to achieve this?

I searched https://veripool.org/verilog-mode/help/ and verilog-auto-inst-sort isn't what I need.

It changes the order in Outputs and Inputs list, but still separate into two groups.

Did some further research and find out it might be something with interface from system-verilog.

    module_a U_A(/*AUTOINST*/);
        
    interface_io U_IF(clk);

    interface interface_io;
        modport A(
            input i1 ,
            output [31:0] o1
        );  
        modport B(
            input i2 ,
            output [31:0] o2
        );  
    endinterface

However, it results in this, similar to implementation in 2010 https://github.com/veripool/verilog-mode/issues/270

    module_a U_A(/*AUTOINST*/
         // Interfaces
         .U_IFA         (U_IFA.A),
         .U_IFB         (U_IFB.B));

I was expecting something like this, which is what I want.

    module_a U_A(/*AUTOINST*/
         // U_IFA Interface
          .i1           (i1),
          .o1           (o1[31:0]),
         // UIFB Interface
          .i2           (i2),
          .o2           (o2[31:0]));

Answer 1

TL:DR Someone is already trying to add this feature, just wait.

Someone already created an issue asking the exact same question.

https://github.com/veripool/verilog-mode/issues/1745

The contributor's answer as followed.

No, because the // Input and // Output comments are "magic" so they need to be in that order. Sorry.

According to this answer, the best result I can expect would be like this.

    module_a U_A(/*AUTOINST*/
         // U_IFA Interface
           // Inputs
          .i1           (i1),
           // Outputs
          .o1           (o1[31:0]),
         // UIFB Interface
           // Inputs
          .i2           (i2),
           // Outputs
          .o2           (o2[31:0]));

Another people also created a similar issue, saying he/she would give it a try to add this feature. I'll count on him/her.

https://github.com/veripool/verilog-mode/issues/1816