In my sw line, it says that it is too few or incorrect operands. I thought that I was storing the character in the position of char_pos. char_pos is ...

I implemented a RV32IM assembly program from the following c-code given that data are 32-bit integers (a, X, Y, and Z are 32-bit long). I verified my ...

I'm hoping to use the CH32V003 (an RV32EC processor) to do ColorChord, which makes extensive use of multiply-add's to perform DFTs. But it can operate ...

In the middle of this page (https://github.com/ultraembedded/riscv), there is a block diagram about the core, I really do not know what is TCM doing i ...

I got the following code : int *heap_x_test = (int*) malloc(4*sizeof(int)); heap_x_test[0] = 0x00310033 ; // add zero,sp,gp heap_x_tes ...

I am trying to analyze the code of fetch.v file from (https://github.com/ultraembedded/riscv/tree/master/core/riscv), but the designer has no document ...

MARS & RARS contain a disassembler, but don't allow .word within .text will only disassemble the .text section Is there a way to get thes ...

I have wrote a riscv64 emulator but I have an issue on offset calculation for branch instructions (especially for bge). For me , the formula to calcu ...

I'm trying to link two risc-v elf files together with ld.lld, but ld.lld is giving me the following error: I suppose that I need to link my files w ...

I'm trying to write the following code : #define CONFIG_PMP_SLOTS 16 #define PMPCFG_STRIDE 4 #define CSR_PMPCFG_BASE 0x3a0 void csr_pmp_check(){ ...

I'm working on translating MIPS assembly programs written for the MARS simulator into RISCV assembly for RARS simulator. This program is to divide th ...

li rd, immediate | Myriad sequences | Load immediate In the RISC-V unprivileged manual, it wrote that there is this pseudoinstruction calles li or Loa ...

What happens on a RISC-V CPU when the program counter (PC) overflows? For example, what happens on RV32G IALIGN = 32 after a (32-bit) NOP at 0xF ...

I'm trying to copy array elements from one array to another. One of the arrays uses a int32_t index to track the current index. If the line is ac ...

First I synthesized a CPU that supports RISCV32IM using verilog, but I can't test if the CPU is working properly. I hope a compiler(such as GCC) can g ...

I have a binary generated with help of LLVM from Halide project. to keep the story short, the binary uses RVV 1.0 while my hardware is AllWinner D1 C9 ...

I'm quite new to inline assembly, so I need your help to be sure that I use it correctly. I need to add assembly code inside my C code that is compile ...

I am working on a project which requires me to generate asm code from llvm ir. When I using llc to generate code directly from .ll file, the assembly ...

I m triying to do a bigger number printer with risc-v. But i cannot implement that. What is not going in my code? ...

I know MIPS ISA out of the box has syscall instruction that can be used to print characters, open files, read from file, write to file and more. This ...