![](/img/trans.png)
[英]Bad operand types 'std_ulogic' and 'string(1 to 1)' from vhdl
[英]VHDL adding 2 std_ulogic_vector does not have any effect
我从VHDL开始,遇到了一些麻烦。
我试图实现双重涉猎算法,将输入的二进制字符串转换为bcd代码。
为此,我已经像在Wiki或其他参考文献中那样实现了它。 但是,我有一个问题
bcdVec(3 downto 0) <= std_ulogic_vector(unsigned(bcdVec(3 downto 0)) + unsigned(three));
没有任何效果(三= std_ulogic_vector(3到0):=“ 0011”)。 在计算之前和之后,我已经使用报告语句对它进行了测试,但结果却相同。
at 210 ns(1): Note: 7 (/bcd_conversion_tb/uut/).
at 210 ns(1): Note: 7 (/bcd_conversion_tb/uut/).
也许有人对我有很好的提示,谢谢!
如果有帮助,这里是整个过程的代码:
BCDProc: process(Reset, CLK_50M) is
begin
if(Reset = ResetLevel) then
working <= '0';
i <= 0;
ready <= '1';
busy <= '0';
bcdVec <= (others => '0');
binVec <= binaryvec;
hundrets_BCD <= (others => '0');
tens_BCD <= (others => '0');
ones_BCD <= (others => '0');
elsif (CLK_50M'event AND CLK_50M = '1') then
if(start = '1') then
working <= '1';
ready <= '0';
end if;
if(i = 7) then
-- split vector to matching BCD values
ones_BCD <= std_ulogic_vector(bcdVec(3 downto 0));
tens_BCD <= std_ulogic_vector(bcdVec(7 downto 4));
hundrets_BCD <= std_ulogic_vector(bcdVec(11 downto 8));
i <= 0;
tmp <= 0;
ready <= '1';
busy <= '0';
working <= '0';
end if;
if (i < 8 AND working = '1') then
busy <= '1';
--check if bcd value is >4, if so then add 3
if(i < 8 AND bcdVec (3 downto 0) > "0100") then
report tmp'image(to_integer(unsigned(bcdVec(3 downto 0))));
bcdVec(3 downto 0) <= std_ulogic_vector(unsigned(bcdVec(3 downto 0)) + unsigned(three));
report tmp'image(to_integer(unsigned(bcdVec(3 downto 0))));
end if;
if(i < 8 AND bcdVec (7 downto 4) > "0100") then
tmp <= to_integer(unsigned(bcdVec(7 downto 4)));
tmp <= tmp + 3;
bcdVec(7 downto 4) <= std_ulogic_vector(to_unsigned(tmp, 4));
end if;
if(i < 8 AND bcdVec (11 downto 8) > "0100") then
tmp <= to_integer(unsigned(bcdVec(11 downto 8)));
tmp <= tmp + 3;
bcdVec(11 downto 8) <= std_ulogic_vector(to_unsigned(tmp, 4));
end if;
--perform the shiftoperations
bcdVec(11 downto 0) <= bcdVec (10 downto 0) & binVec(7);
binVec(7 downto 0) <= binVec(6 downto 0) & '0';
--increment countervariable
i <= i+1;
end if;
end if;
end process BCDProc;
在进程挂起之前,信号分配永远不会更新。 此过程仅在其敏感度列表处暂停。 因此,您随后的tmp快照不会将bcdVec加3,而是将tmp值加3到该过程的最后一次执行-即:CLK_50M的上一个上升沿。
if(i < 8 AND bcdVec (11 downto 8) > "0100") then
tmp <= to_integer(unsigned(bcdVec(11 downto 8)));
tmp <= tmp + 3;
bcdVec(11 downto 8) <= std_ulogic_vector(to_unsigned(tmp, 4));
end if;
您在整个过程中都会做类似的事情。 例如,如果开始为“ 1”,则计划将工作设置为“ 1”,然后如果“ i = 7”,则覆盖该值,
if(start = '1') then
working <= '1';
ready <= '0';
end if;
if(i = 7) then
. . .
working <= '0';
end if;
然后,您稍后尝试进行测试以查看是什么(以下摘录),但是该过程尚未挂起,因此work的值尚未更新,并且仍具有上一次执行时的值。
if (i < 8 AND working = '1') then
声明:本站的技术帖子网页,遵循CC BY-SA 4.0协议,如果您需要转载,请注明本站网址或者原文地址。任何问题请咨询:yoyou2525@163.com.