[英]Verilog 4-bit carry select adder
因此,我尝试在verilog中设计一个4位进位选择加法器,并在设计中使用以下代码:
module fullAdder (S,Cout,P,G,A,B,Cin);
// Define all inputs and outputs for single bit Fulll Adder
output S;
output Cout;
output P;
output G;
input A;
input B;
input Cin;
// Full Adder body, define structure and internal wiring
wire t1, t2, t3;
xor xor1 (t1, A, B);
xor xor2 (S, t1, Cin);
or or1 (P, A, B);
and and1 (G, A, B);
and and2 (t2, P, Cin);
or or2 (Cout, t2, G);
endmodule
module carrySelect (sum, cout, a, b, cin);
output [3:0] sum; //sum output of the adder, 4 bits wide
output cout; //carry out of the adder
input [3:0] a; //input a, 4 bits wide
input [3:0] b; //input b, 4 bits wide
input cin; //carry in of the adder
reg ch, cl; //temporary variables to define cases that previous carry is high or low
wire [3:0] C; //carry bus
wire [3:0] P,G; //buses for P and G outputs of fullAdder
wire [1:0] s0, s1, s2, s3; //temporary buses for cases of sums
wire [1:0] c0, c1, c2, c3; //temporary buses for cases of carries
assign ch = 1; //assign ch to high and cl to low
assign cl = 0;
//least significant full adder computation
fullAdder f0_h (s0[0],c0[0],p0[0], g0[0], a[0], b[0], ch);
fullAdder f0_l (s0[1],c0[1],p0[1], g0[1], a[0], b[0], cl);
fullAdder f1_h (s1[0],c1[0],p1[0], g1[0], a[0], b[0], ch);
fullAdder f1_l(s1[1],c1[1],p1[1], g1[1], a[0], b[0], cl);
fullAdder f2_h (s2[0],c2[0],p2[0], g2[0], a[0], b[0], ch);
fullAdder f2_l (s2[1],c2[1],p2[1], g2[1], a[0], b[0], cl);
//most significant full adder computation
fullAdder f3_h (s3[0],c3[0],p3[0], g3[0], a[0], b[0], ch);
fullAdder f3_l (s3[1],c3[1],p3[1], g3[1], a[0], b[0], cl);
//select output depending on values of carries
if (cin == 1) begin
assign sum[0] = s0[0];
assign C[0] = c0[0];
end else begin
assign sum[0] = s0[1];
assign C[0] = c0[1];
end
if(C[0] == 1) begin
assign sum[1] = s1[0];
assign C[1] = c1[0];
end else begin
assign sum[1] = s1[1];
assign C[1] = c1[1];
end
if(C[1]) begin
assign sum[2] = s2[0];
assign C[2] = c2[0];
end else begin
assign sum[2] = s2[1];
assign C[2] = c2[1];
end
if(C[2]) begin
assign sum[3] = s3[0];
assign C[3] = c3[0];
end else begin
assign sum[3] = s3[1];
assign C[3] = c3[1];
end
//assign carry out
assign cout = C[3];
endmodule
完整的加法器完全可以正常工作,因此那里没有问题。 当我尝试编译代码时,我从if语句中得到错误,并得到有关隐式定义的警告和无法在ifs中评估条件的genvar的错误。 我对verilog还是很陌生,所以如果这是个小问题,我深表歉意。 任何帮助表示赞赏。
EDIT1:引发错误/警告消息
design.sv:57: warning: implicit definition of wire fullAdderTest.UUT.cin.
design.sv:57: error: Cannot evaluate genvar conditional expression: (cin)==('sd1)
design.sv:57: error: Cannot evaluate genvar conditional expression: (cin)==('sd1)
design.sv:65: warning: implicit definition of wire fullAdderTest.UUT.C.
design.sv:65: error: Cannot evaluate genvar conditional expression: (C['sd0])==('sd1)
design.sv:65: error: Cannot evaluate genvar conditional expression: (C['sd0])==('sd1)
design.sv:73: warning: Constant bit select [1] is after vector C[0:0].
design.sv:73: : Replacing select with a constant 1'bx.
design.sv:73: warning: Constant bit select [1] is after vector C[0:0].
design.sv:73: : Replacing select with a constant 1'bx.
design.sv:81: warning: Constant bit select [2] is after vector C[0:0].
design.sv:81: : Replacing select with a constant 1'bx.
design.sv:81: warning: Constant bit select [2] is after vector C[0:0].
design.sv:81: : Replacing select with a constant 1'bx.
4 error(s) during elaboration.
一个if
一个外部声明always
或initial
块被视为好像它是一个内部generate
块。 生成的if语句将接受文字常量(硬编码值),参数和genvar。 它将不接受网络或寄存器类型(即: wire
, reg
, integer
等)。 生成块在详细说明期间进行评估,因此不能依赖具有动态值的模拟变量。
您需要根据输入值有条件地选择sum
和C
的值。 有几种方法可以做到这一点:
一种选择是做出内联条件语句:
assign sum[0] = cin ? s0[0] : s0[1];
assign C[0] = cin ? c0[0] : c0[1];
// ...
或者,您可以选择索引(效果相同):
assign sum[0] = s0[!cin];
assign C[0] = c0[!cin];
assign sum[1] = s1[!C[0]];
assign C[1] = c1[!C[0]];
// ...
或者创建sum
和C
reg
类型,并将所有if语句放入always块中(删除assign
):
always @* begin
if (cin == 1) begin
sum[0] = s0[0];
C[0] = c0[0];
end
else begin
sum[0] = s0[1];
C[0] = c0[1];
end
// ...
end
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