使用案例声明的JK触发器的VHDL程序

Question

library ieee;
use ieee. std_logic_1164.all;
 entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin

process(clock,j,r)

begin
jk <= j & k;
if(clock= '1' and clock'event) then
 case (jk) is
   when "00" => temp<= temp;
   when "01" => temp <= '0';
   when "10" => temp <= '1';
   when "11" => not temp;
   when others => temp <= 'X'
end case;
end process;
q <= temp;
qbar <= not temp;

end behavioral;

当我使用ghdl编译该程序时，它显示错误“何时”而不是“不是”。 请帮助我找到此代码的问题。

Answer 1

您忘记了这些东西：

1） when "11" => not temp; when "11" => temp <= not temp;

2） when others => temp <= 'X'时，结尾处必须有分号when others => temp <='X';

3） end if在end if末尾错过了结尾

4）过程灵敏度列表包含一个未声明的名为“ r”的信号

由于在if语句中执行的所有代码都仅受时钟限制，因此我从流程中省略了信号j和k，因此，当j和k更改其值并且时钟为0时，无需执行该过程。不在上升边缘。

library ieee;
use ieee. std_logic_1164.all;
 entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin

process(clock)

begin
jk <= j & k;
if(clock= '1' and clock'event) then
   case (jk) is
     when "00" => temp<= temp;
     when "01" => temp <= '0';
     when "10" => temp <= '1';
     when "11" => temp <= not temp;
     when others => temp <= 'X';
    end case;
end if;
end process;
q <= temp;
qbar <= not temp;

end behavioral;