使用案例聲明的JK觸發器的VHDL程序

Question

library ieee;
use ieee. std_logic_1164.all;
 entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin

process(clock,j,r)

begin
jk <= j & k;
if(clock= '1' and clock'event) then
 case (jk) is
   when "00" => temp<= temp;
   when "01" => temp <= '0';
   when "10" => temp <= '1';
   when "11" => not temp;
   when others => temp <= 'X'
end case;
end process;
q <= temp;
qbar <= not temp;

end behavioral;

當我使用ghdl編譯該程序時，它顯示錯誤“何時”而不是“不是”。 請幫助我找到此代碼的問題。

Answer 1

您忘記了這些東西：

1） when "11" => not temp; when "11" => temp <= not temp;

2） when others => temp <= 'X'時，結尾處必須有分號when others => temp <='X';

3） end if在end if末尾錯過了結尾

4）過程靈敏度列表包含一個未聲明的名為“ r”的信號

由於在if語句中執行的所有代碼都僅受時鍾限制，因此我從流程中省略了信號j和k，因此，當j和k更改其值並且時鍾為0時，無需執行該過程。不在上升邊緣。

library ieee;
use ieee. std_logic_1164.all;
 entity JKFF is
PORT( j,k,clock: in std_logic;
q,qbar: out std_logic);
end JKFF;
Architecture behavioral of JKFF is
signal jk : std_logic_vector(1 downto 0);
signal temp : std logic;
begin

process(clock)

begin
jk <= j & k;
if(clock= '1' and clock'event) then
   case (jk) is
     when "00" => temp<= temp;
     when "01" => temp <= '0';
     when "10" => temp <= '1';
     when "11" => temp <= not temp;
     when others => temp <= 'X';
    end case;
end if;
end process;
q <= temp;
qbar <= not temp;

end behavioral;