[英]Does 64-bit RISC-V RV64 allow access to the low 32 bits of registers?
[英]RV32IM assembly for 64-bit value
假设数据是32 位整数(a、X、Y 和 Z 是 32 位长),我从以下 C 代码实现了一个 RV32IM 汇编程序。 我验证了我的工作,结果是正确的。
#define W 20
int main() {
int X[W] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19};
int Y[W] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
int Z[W];
int a=2;
iaXpY(a, X, Y, Z);
return 0;
};
void iaXpY(int a, int *X, int *Y, int *Z) {
register int i=0;
for (int i = 0; i < W; i++) {
Z[i] = a*X[i] + Y[i];
}
}
我的 32 位数据工作
# iaXpY program, implementation in RV32IM assembly
# for(i=0; i<W, i=i++) Z[i] = a*X[i] + Y[i];
.data
X: .word 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19
Y: .word 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
Z: .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
W: .word 20
a: .word 2
.text
# a0 = a
# a1 = X base address
# a2 = Y base address
# a3 = Z base address
# s1 = W
# t0 = i
# t1 = a*X[i] + Y[i]
main:
lw a0, a # a0 = a
lw s1, W # s1 = W
la a1, X # a1 = &X
la a2, Y # a2 = &Y
la a3, Z # a3 = &Z
jal ra, iaXpY # jump to for loop
li a7, 10 # end program
ecall
iaXpY:
add t0, x0, x0 # i = 0
loop:
# scheduled to avoid data hazards
lw t1, 0(a1) # t1 = X[i]
addi a1, a1, 4 # ++X
mul t1, t1, a0 # t1 = a*X[i]
lw t2, 0(a2) # t2 = Y[i]
addi a2, a2, 4 # ++Y
add t1, t1, t2 # t1 = a*X[i] + Y[i]
addi t0, t0, 1 # i++
sw t1, 0(a3) # Z[i] = a*X[i] + Y[i]
addi a3, a3, 4 # ++Z
blt t0, s1, loop # if i < W, go to loop
ret # else, return to main
现在, Implement with data 是64-bit integer (a, X, Y, Z are 64-bit long),但仍然使用 RV32IM。 我的做法是,由于RV32IM中一个寄存器只能存放32位的值,所以我必须用两个寄存器来存放高32位和低32位,但是在RV32IM汇编中如何实现呢?
64 位“整数”不等同于“长”吗? 我认为使用“长”数据类型而不是“整数”来编译 C 代码将为您提供所需的汇编代码。
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