VHDL-写入FPGA寄存器

Question

我有一个带有四个按钮的FPGA-最左边的两个按钮应在16个寄存器之间循环，而最右边的两个按钮应使该寄存器中存储的值递增或递减。 这是我尝试执行此操作的代码：

entity raminfr is   --inferring the RAM here
    port (
        clk : in std_logic;
        we : in std_logic;
        a : in unsigned(3 downto 0);
        di : in unsigned(7 downto 0);
        do : out unsigned(7 downto 0)
    );
end raminfr;

architecture rtl of raminfr is

type ram_type is array (0 to 15) of unsigned(7 downto 0);
signal RAM : ram_type;
signal read_a : unsigned(3 downto 0);

begin
  U1: entity work.lab1 port map (  --ERROR ON THIS LINE
    register_counter => a,
    value_counter => di
  );
process (clk)
begin
    if rising_edge(clk) then
        if we = '1' then
            RAM(to_integer(a)) <= di;
        end if;
        read_a <= a;
    end if;
end process;
do <= RAM(to_integer(read_a));
end rtl;




--lab1 starts here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lab1 is 
    port(
        clock : in std_logic;
        key : in std_logic_vector(3 downto 0); 
        value_counter   : out unsigned(7 downto 0) ; --value to be written to register
        register_counter : out unsigned(3 downto 0) --register to write value to

        );
end lab1;

architecture up_and_down of lab1 is --actual button logic here
        begin
    process(clock)
        begin
            if rising_edge(clock) then
                if (key(3)='0' and key(2)='0' and key(1)='1' and key(0)='0') then
                    value_counter <= value_counter + "1";   
                elsif (key(3)='0' and key(2)='0' and key(1)='0' and key(0)='1') then  
                    value_counter <= value_counter - "1";
                elsif (key(3)='1' and key(2)='0' and key(1)='0' and key(0)='0') then
                    register_counter<= register_counter + "1";
                elsif (key(3)='0' and key(2)='1' and key(1)='0' and key(0)='0') then
                    register_counter<= register_counter - "1";
                end if;
            end if;
    end process;
end architecture up_and_down;

我收到错误Error (10577): VHDL error at DE2_TOP.vhd(312): actual port "a" of mode "in" cannot be associated with formal port "register_counter" of mode "out"上述行Error (10577): VHDL error at DE2_TOP.vhd(312): actual port "a" of mode "in" cannot be associated with formal port "register_counter" of mode "out" 。 显然，这不是我要做自己想做的事情。 有人可以阐明这一点吗？

Answer 1

改变您的观点：将RAM放在Pushbutton-FSM下。 反之亦然。

该RAM描述应该是可综合的。 如果没有，请查看您的工具供应商的综合指南。

entity raminfr is   --inferring the RAM here
    port (
        clk : in  std_logic;
        we  : in  std_logic;
        a   : in  unsigned(3 downto 0);
        di  : in  unsigned(7 downto 0);
        do  : out unsigned(7 downto 0)
    );
end entity raminfr;

architecture rtl of raminfr is

type ram_type is array (0 to 15) of unsigned(7 downto 0);
signal RAM : ram_type;

begin
  process (clk)
  begin
    if rising_edge(clk) then
        if we = '1' then
            RAM(to_integer(a)) <= di;
        end if;
        do <= RAM(to_integer(a));
    end if;
  end process;
end architecture rtl;

您还忘记了激活RAM的写使能。 也许您可以尝试以下代码（始终首先进行模拟！）：

--lab1 starts here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lab1 is 
  port(
    clock            : in std_logic;
    key              : in std_logic_vector(3 downto 0); 
    value_counter    : out unsigned(7 downto 0); --value to be written to register
    ram_data         : out unsigned(7 downto 0); --value from 'RAM-register'
    register_counter : out unsigned(3 downto 0) --register to write value to
  );
end lab1;

architecture up_and_down of lab1 is --actual button logic here
  signal value    : unsigned(7 downto 0) := (others => '0');
  signal ram_a    : unsigned(3 downto 0) := (others => '0');
  signal ram_we   : std_logic;

begin

  -- infer your RAM
  your_ram:  entity work.raminfr
    port map (
      clk => clock,   --: in  std_logic;
      we  => ram_we,  --: in  std_logic;
      a   => ram_a,   --: in  unsigned(3 downto 0);
      di  => value,   --: in  unsigned(7 downto 0);
      do  => ram_data --: out unsigned(7 downto 0)
    );

  process(clock)
  begin
    if rising_edge(clock) then
      -- default
      ram_we <= '0';

      -- change value
      if key(1) = '1' then
        value <= value + 1;
      end if;

      -- change value
      if key(0) = '1' then
        value <= value - 1;
      end if;

      -- change 'register'
      if key(3) = '1' then
        ram_a  <= ram_a + 1;
      end if;

      -- write value to register
      if key(2) = '1' then
        ram_we <= '1';
      end if;
    end if;
  end process;

  value_counter    <= value;
  register_counter <= ram_a;

end architecture up_and_down;