[英]Integer or not, in vhdl
有什么辦法可以做到這一點:
Comp : in STD_LOGIC_VECTOR (7 downto 0);
EP : in STD_LOGIC_VECTOR (2 downto 0);
(......)
signal pos : STD_LOGIC_VECTOR (7 downto 0):=(OTHERS => '0');
--signal i : STD_LOGIC_VECTOR (2 downto 0):=(OTHERS => '0');
(......)
--i<=EP;
IF(Comp(to_integer(unsigned(EP)))='1') then
pos(to_integer(unsigned(EP)))<='1';
elsif(Comp(to_integer(unsigned(EP-"001")))='1') then
pos(to_integer(unsigned(EP-"001")))<='1';
elsif(Comp(to_integer(unsigned(EP-"010")))='1') then
pos(to_integer(unsigned(EP-"010")))<='1';
elsif(Comp(to_integer(unsigned(EP-"011")))='1') then
pos(to_integer(unsigned(EP-"011")))<='1';
elsif(Comp(to_integer(unsigned(EP-"100")))='1') then
pos(to_integer(unsigned(EP-"100")))<='1';
elsif(Comp(to_integer(unsigned(EP-"101")))='1') then
pos(to_integer(unsigned(EP-"101")))<='1';
elsif(Comp(to_integer(unsigned(EP-"110")))='1') then
pos(to_integer(unsigned(EP-"110")))<='1';
else
pos(to_integer(unsigned(EP-"111")))<='1';
end if;
我收到錯誤消息:to_integer在這種情況下不能有這樣的操作數。 我該如何解決?
您只是在錯誤的位置將右括號括起來,將ep
轉換為unsigned:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity foo is -- imaginary entity
port (
comp: in std_logic_vector (7 downto 0);
ep: in std_logic_vector (2 downto 0)
);
end entity;
architecture imaginary of foo is
signal pos : std_logic_vector (7 downto 0):=(others => '0');
--signal i : std_logic_vector (2 downto 0):=(others => '0');
begin
IMAGINARY_PROCESS:
process
begin
if comp ( to_integer(unsigned(ep)) ) = '1' then
pos( to_integer(unsigned(ep)) ) <= '1';
elsif comp( to_integer(unsigned(ep) - "001") )='1' then
pos( to_integer(unsigned(ep) - "001") ) <= '1';
elsif comp( to_integer(unsigned(ep) - "010") ) = '1' then
pos( to_integer(unsigned(ep) - "010") ) <= '1';
elsif comp( to_integer(unsigned(ep) - "011") ) = '1' then
pos( to_integer(unsigned(ep) - "011") ) <= '1';
elsif comp( to_integer(unsigned(ep) - "100") ) = '1' then
pos( to_integer(unsigned(ep) - "100") ) <= '1';
elsif comp( to_integer(unsigned(ep) - "101") ) = '1' then
pos( to_integer(unsigned(ep) - "101") ) <= '1';
elsif comp( to_integer(unsigned(ep) - "110") ) = '1' then
pos( to_integer(unsigned(ep) - "110") ) <= '1';
else
pos( to_integer(unsigned(ep) - "111") ) <= '1';
end if;
end process;
end architecture;
當您遵循一致的格式和縮進時,將更易於檢測。
提供應該分析的測試用例並不難。
對於您的注釋,Shekar的回答“所有這些:to_integer不能擁有...”應該是除第一個以外的所有內容,它還證明了足以分析的示例代碼的價值(即使不正確) 。
確保在模塊頂部使用正確的軟件包。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
還要確保您不要嘗試使用std_logic_arith
或std_logic_unsigned
軟件包。
請參閱David Koontz關於放錯括號的答案。 如果使用正確的軟件包,則將無法直接在std_logic_vector
上進行數學運算。
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