[英]Comparing integer values for assignment to a std_logic_vector
我有一個范圍為 0 到 23 的整數數組,它存儲范圍為 0 到 2 的值,例如:
type t_slave_24symbol is array (0 to 23) of integer range 0 to 2;
signal slave_24symbol : t_slave_24symbol;
type nibble_array is array (0 to 7) of STD_LOGIC_VECTOR(3 downto 0);
signal nibble : nibble_array;
signal nibble_full : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
現在我想將此字符串拆分為 3 個序列並進行比較
nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
"0001" when slave_24symbol(012)= 200 else
"0010" when slave_24symbol(012)= 020 else
"1111";
但后來
nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
. . .
最后
nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
& nibble(5) & nibble(6) & nibble(7);
我該怎么辦? 因為我想分配 char 9 10 和 11 等等。
該問題顯示了python語法思維。
有一個受約束的整數數組被轉換為 std_logic_vector 數組中的二進制表示。
首先是分配一個半字節元素的最小、完整和可驗證示例:
library ieee;
use ieee.std_logic_1164.all;
entity depython is
end entity;
architecture foo of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
begin
-- nibble(0) <= "0000" when slave_24symbol(012) = 120 else--
-- "0001" when slave_24symbol(012)= 200 else
-- "0010" when slave_24symbol(012)= 020 else
-- "1111";
-- BECOMES:
nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1, 2, 0) else
"0001" when slave_24symbol(0 to 2) = nyyblet'(2, 0, 0) else
"0010" when slave_24symbol(0 to 2) = nyyblet'(0, 2, 0) else
"1111";
end architecture;
類型t_slave_24symbol
已更改為不受約束的數組定義,並聲明了信號slave_24symbol
提供了子類型。 (這在 -2008 年稱為無界數組定義)。
slave_24symbol
切片的索引范圍更改為 VHDL 語法。 在每個條件中評估的表達式的值范圍已更改為使用聚合的 VHDL 語法,聚合的類型由需要子類型定義的合格表達式提供。 子類型聲明需要無約束/無界數組定義。
需要限定表達式來指定子類型,因為數組類型的預定義相等運算符對不受約束的操作數進行操作 - 您可以測試兩個不同長度數組的相等性,它們將始終不相等。 (在處理空數組時派上用場)。
請注意,字符串文字的類型(例如“0010”)由上下文決定,元素值('0'、'1')必須與數組類型(此處為 std_logic_vector)的元素類型(此處為 std_ulogic)兼容。
這里分析、闡述和模擬(對slave_24symbol的每個元素使用默認值(0, 0, 0),每個進程在初始化時都會執行一次,並發賦值語句被闡述為包含在進程語句中的等效順序賦值語句) .
現在我們討論如何在新架構中轉換所有nibble
元素:
architecture sequential of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
function nybble (nyb: nyyblet) return std_logic_vector is
-- retv: std_logic_vector(3 downto 0);
begin
if nyb = nyyblet'(1, 2, 0) then
return "0000";
elsif nyb = nyyblet'(2, 0, 0) then
return "0001";
elsif nyb = nyyblet'(0, 2, 0) then
return "0010";
else
return "1111";
end if;
end function;
begin
-- nibble(0) <= "0000" when slave_24symbol(0 to 2) = nyyblet'(1,2,0) else
-- "0001" when slave_24symbol(0 to 2) = nyyblet'(2,0,0) else
-- "0010" when slave_24symbol(0 to 2) = nyyblet'(0,2,0) else
-- "1111";
-- but later
--
-- nibble(3) <= "0000" when slave_24symbol(91011) = 012 else
--
-- . . .
--
-- and at the end
--
-- nibble_full <= nibble(0) & nibble(1) & nibble(2) & nibble(3) & nibble(4)
-- & nibble(5) & nibble(6) & nibble(7);
process (slave_24symbol)
begin
for i in nibble'range loop
nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
end loop;
end process;
end architecture;
這里使用了一個函數調用來隱藏一些復雜性。 循環語句中的順序賦值語句(順序語句本身)使用偏移算術來尋址被評估的slave_24symbol
的三個約束整數的所有八個切片。
並且因為問題顯示在條件信號分配(這里是並發信號分配)中分配了一個半字節元素,所以使用生成語句的並發分配版本:
architecture concurrent of depython is
type t_slave_24symbol is array (natural range <>) of integer range 0 to 2;
signal slave_24symbol: t_slave_24symbol (0 to 23);
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
signal nibble: nibble_array;
signal nibble_full: std_logic_vector(31 downto 0) := (others => '0');
subtype nyyblet is t_slave_24symbol (0 to 2);
function nybble (nyb: nyyblet) return std_logic_vector is
-- retv: std_logic_vector(3 downto 0);
begin
if nyb = nyyblet'(1, 2, 0) then
return "0000";
elsif nyb = nyyblet'(2, 0, 0) then
return "0001";
elsif nyb = nyyblet'(0, 2, 0) then
return "0010";
else
return "1111";
end if;
end function;
begin
-- process (slave_24symbol)
-- begin
-- for i in nibble'range loop
-- nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
-- end loop;
-- end process;
NIBBLE_IT:
for i in nibble'range generate
nibble(i) <= nybble(slave_24symbol(3 * i to 2 + i * 3));
end generate;
end architecture;
所有顯示的架構都分析、闡述和模擬,證明所有索引和切片都在子類型范圍內。
請注意,您還可以將循環語句倒入參數類型為t_slave_24symbol
的函數中,並同時或按順序執行一個賦值。 這也將允許檢測不是由 3 個整數的倍數組成的參數值(因為類型t_slave_24symbol
被聲明為無約束/無界)。 通過聲明新類型並創建新類型的t_slave_24symbol
和nyyblet
子類型,可以避免任何參數值檢測:
architecture all_in_one_function of depython is
type c_integer_array is array (natural range <>) of integer range 0 to 2;
subtype t_slave_24symbol is c_integer_array (0 to 23);
signal slave_24symbol: t_slave_24symbol := (
1,2,0, 2,0,0, 0,2,0, 0,0,0, 0,0,1, 0,0,2, 0,1,0, 0,1,1);
signal nibble_full: std_logic_vector (31 downto 0);
function nybble (slave: t_slave_24symbol) return std_logic_vector is
type nibble_array is array (0 to 7) of std_logic_vector(3 downto 0);
variable nib: nibble_array;
subtype nyyblet is c_integer_array (0 to 2);
begin
for i in nib'range loop
if slave(3 * i to 2 + i * 3) = nyyblet'(1, 2, 0) then
nib(i) := "0000";
elsif slave(3 * i to 2 + i * 3) = nyyblet'(2, 0, 0) then
nib(i) := "0001";
elsif slave(3 * i to 2 + i * 3) = nyyblet'(0, 2, 0) then
nib(i) := "0010";
else
nib(i) := "1111";
end if;
end loop;
return nib(0) & nib(1) & nib(2) & nib(3) &
nib(4) & nib(5) & nib(5) & nib(7);
end function;
function to_string (inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end function;
begin
NIBBLE_IT:
nibble_full <= nybble(slave_24symbol);
process
begin
wait for 0 ns;
report "nibble_full = " & to_string (nibble_full);
wait;
end process;
end architecture;
添加 to_string 函數是為了與 -2008 之前的 VHDL 版本兼容。 信號_slave_24symbol
被初始化以證明轉換成功:
/usr/local/bin/ghdl -a depython1.vhdl
/usr/local/bin/ghdl -e depython
/usr/local/bin/ghdl -r depython
depython1.vhdl:79:9:@0ms:(report note): nibble_full = 000000010010111111111111111111111
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