如何為切片輸出信號賦值？

Question

我是 myhdl 的初學者。 我嘗試將以下 Verilog 代碼轉換為 MyHDL：

module ModuleA(data_in, data_out, clk);
    input data_in;
    output reg data_out;
    input clk;

    always @(posedge clk) begin
        data_out <= data_in;
    end
endmodule

module ModuleB(data_in, data_out, clk);
    input [1:0] data_in;
    output [1:0] data_out;
    input clk;

    ModuleA instance1(data_in[0], data_out[0], clk);
    ModuleA instance2(data_in[1], data_out[1], clk);
endmodule

目前，我有這個代碼：

import myhdl

@myhdl.block
def ModuleA(data_in, data_out, clk):
    @myhdl.always(clk.posedge)
    def logic():
        data_out.next = data_in

    return myhdl.instances()


@myhdl.block
def ModuleB(data_in, data_out, clk):
    instance1 = ModuleA(data_in(0), data_out(0), clk)
    instance2 = ModuleA(data_in(1), data_out(1), clk)

    return myhdl.instances()


# Create signals
data_in = myhdl.Signal(myhdl.intbv()[2:])
data_out = myhdl.Signal(myhdl.intbv()[2:])
clk = myhdl.Signal(bool())

# Instantiate the DUT
dut = ModuleB(data_in, data_out, clk)

# Convert tfe DUT to Verilog
dut.convert()

但它不起作用，因為信號切片會產生只讀陰影信號（參見MEP-105 ）。 那么，在 MyHDL 中擁有可寫信號片段的好方法是什么？

編輯：這是我得到的錯誤

$ python demo.py
Traceback (most recent call last):
File "demo.py", line 29, in <module>
    dut.convert()
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/_block.py", line 342, in convert
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/conversion/_toVerilog.py", line 177, in __call__
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/conversion/_analyze.py", line 170, in _analyzeGens
File "/usr/lib/python3.6/ast.py", line 253, in visit
    return visitor(node)
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/conversion/_analyze.py", line 1072, in visit_Module
File "/home/killruana/.local/share/virtualenvs/myhdl_sandbox-dYpBu4o5/lib/python3.6/site-packages/myhdl-0.10-py3.6.egg/myhdl/conversion/_misc.py", line 148, in raiseError
myhdl.ConversionError: in file demo.py, line 4:
    Signal has multiple drivers: data_out

Answer 1

您可以使用 Signal(bool()) 的中間列表作為占位符。

@myhdl.block
def ModuleB(data_in, data_out, clk):
    tsig = [myhdl.Signal(bool(0)) for _ in range(len(data_in))]

   instances = []
   for i in range(len(data_in)):
        instances.append(ModuleA(data_in(i), tsig[i], clk))

   @myhdl.always_comb
   def assign():
        for i in range(len(data_out)):
            data_out.next[i] = tsig[i]

   return myhdl.instances()

Answer 2

一個快速（可能無法實現）的評論是intbv被視為不能有多個驅動器的單個實體。 兩個可能有助於闡明的參考文獻：

• http://jandecaluwe.com/hdldesign/counting.html
• http://docs.myhdl.org/en/stable/manual/structure.html#converting-between-lists-of-signals-and-bit-vectors