[英]Verilog testbench simulation error
module stimulus;
reg [511:0]FROM_LS;
reg CLOCK;
reg [2:0]HMIC_CTRL;
reg [20:0]BRANCH_CTRL;
reg [63:0]TO_IF_ID;
reg FLUSH_CTRL;
reg [20:0]TO_LS;
inst_line_buf ILB(FLUSH_CTRL,TO_LS,FROM_LS,CLOCK,HMIC_CTRL,BRANCH_CTRL,TO_IF_ID);
// setup clock
initial
begin
#10 CLOCK = ~CLOCK;
// apply stimulus
FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
FROM_LS[479:448]=32'b000_11000_00100_01111_11111_00011_1000;
HMIC_CTRL[2:0]=3'b000;
BRANCH_CTRL[20:0]=20'b00000_00000_00000_00000;
#2 $display("FLUSH CONTROL=%b, TO_LS= %b",FLUSH_CTRL,TO_LS);
end
終端模塊
我收到以下錯誤:
# Loading work.inst_line_buf
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (512 or 512) does not match connection size (1) for port 'from_LS'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(1).
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (21) for port 'clk'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(2).
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (3 or 3) does not match connection size (512) for port 'hmic_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(3).
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (21 or 21) does not match connection size (1) for port 'branch_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(4).
# Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'to_if_id'".
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (64 or 64) does not match connection size (3) for port 'to_if_id'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(5).
# Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'flush_ctrl'".
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (21) for port 'flush_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(6).
# Region: /stimulus/ILB
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'to_LS'".
# Region: /stimulus/ILB
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (21 or 21) does not match connection size (64) for port 'to_LS'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(7).
# Region: /stimulus/ILB
# Error loading design
除非您向我們顯示完整的錯誤消息,您的vsim
命令行以及一些相關的Verilog代碼,否則我們所能提供的只是向Google建議您的錯誤消息。
例如,來自modelsim_FAQ :
未正確設置ModelSim Simulation選項(“項目設置”>“ ModelSim”>“選項”)進行以下更改:在“項目流”窗口中右鍵單擊“模擬”選項卡,或選擇“項目”>“設置”>“模擬” Testbench模塊名稱:指定您的Testbench模塊名稱頂級testbench中的實例名稱:DUT的實例名稱請參見以下屏幕截圖以獲取示例。
更新:現在您已經添加了一些代碼, ILB
看起來很可疑。 首先將它用作inst_line_buf
模塊的實例名稱,然后在initial
塊中再次使用它,就像函數或任務調用一樣。 我的猜測是,您希望它在initial
塊之外,但具有端口連接:
inst_line_buf ILB (FROM_LS,CLOCK,HMIC_CTRL,TO_IF_ID,FLUSH_CTRL,TO_LS);
聲明:本站的技術帖子網頁,遵循CC BY-SA 4.0協議,如果您需要轉載,請注明本站網址或者原文地址。任何問題請咨詢:yoyou2525@163.com.