[英]VHDL textio read file debug
我在調試該程序時遇到了一些麻煩。 我被指派從文本文件中讀取測試向量以測試程序。 程序和測試平台代碼如下所示。 我無法弄清楚為什么我的模擬結果空白。 沒有錯誤,模擬窗口出現,但是它是空白的。 知道可能是什么問題嗎?
模塊:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PAR is
Port ( data : in STD_LOGIC_VECTOR (3 downto 0);
parity : out STD_LOGIC);
end PAR;
architecture Behavioral of PAR is
begin
proc: process
variable count: bit;
begin
for i in data'range loop
if data(i)='1' then
count:=not count;
end if;
end loop;
if count='0' then
parity<='0';
else
parity<='1';
end if;
wait;
end process;
end Behavioral;
試驗台:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.all;
use ieee.std_logic_textio.all;
ENTITY PAR_test IS
END PAR_test;
ARCHITECTURE behavior OF PAR_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PAR
PORT(
data : IN std_logic_vector(3 downto 0);
parity : OUT std_logic
);
END COMPONENT;
--Inputs
signal data : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal parity : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PAR PORT MAP (
data => data,
parity => parity
);
TB: process
file vec_file: text;
variable buf_in: line;
variable testv: std_logic_vector(0 to 4);
begin
file_open(vec_file,"PAR_file.txt,", read_mode);
while not endfile (vec_file) loop
readline (vec_file, buf_in);
read(buf_in,testv);
data(3) <= testv(0);
data(2) <= testv(1);
data(1) <= testv(2);
data(0) <= testv(3);
wait for 10 ns;
assert (parity=testv(4))
report "Test Failed" severity error;
end loop;
wait;
END process;
end;
在“ file_open ..”行中,有一個不需要的“,”
錯誤的是:
file_open(vec_file,"PAR_file.txt,", read_mode);
正確的是:
file_open(vec_file,"PAR_file.txt", read_mode);
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