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[英]Is it possible to use gcc/g++/nvcc automatic dependency -M in a single pass of a Makefile without saving dependencies to a file?
[英]Makefile with multiple targets and automatic dependency generation using g++ -MMD
SO上的另一個問題描述了單個目標的完美優雅的makefile:
CXX = g++ # compiler
CXXFLAGS = -g -Wall -MMD # compiler flags
OBJECTS = x.o y.o z.o # object files forming executable
DEPENDS = ${OBJECTS:.o=.d} # substitutes ".o" with ".d"
EXEC = a.out # executable name
${EXEC} : ${OBJECTS} # link step
${CXX} ${OBJECTS} -o ${EXEC}
-include ${DEPENDS} # copies files x.d, y.d, z.d (if they exist)
我的問題是:我們如何才能針對多個目標進行調整?
您的解決方案看起來不錯,但是如果目標很多,那么擴展起來就容易一點:
EXECS = exec_x exec_y
exec_x: a.o b.o c.o
exec_y: d.o e.o f.o
$(EXECS):
${LINK}
我找到了一個可行的解決方案,但我很想知道這是否合適。
CXX = g++ # compiler
CXXFLAGS = -g -Wall -MMD # compiler flags
LINK = ${CXX} $^ -o $@ # link step
exec_x: a.o b.o c.o
${LINK}
exec_y: d.o e.o f.o
${LINK}
-include *.d
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