[英]Connecting program to module in SystemVerilog
I'm trying to connect between a top level module and a program block in SystemVeilog using interface.我正在尝试使用接口在 SystemVeilog 中的顶级模块和程序块之间进行连接。
I succeed in passing the wires, but I couldn't do it also for the parameters.我成功地传递了电线,但我也无法传递参数。
How can I pass the parameters in the module to the program?如何将模块中的参数传递给程序? Is it possible in any way?有可能吗?
You pass a parameter
to a program
in the same way as you pass one to a module
.将parameter
传递给program
的方式与将parameter
传递给module
方式相同。 Refer to the IEEE Std 1800-2012, Section "24. Programs".请参阅 IEEE Std 1800-2012,“24. 程序”部分。 For example:例如:
module tb;
test #(.WIDTH(8)) test ();
endmodule
program test;
parameter WIDTH = 5;
initial $display("WIDTH = %0d", WIDTH);
endprogram
Output:输出:
WIDTH = 8
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