Connecting program to module in SystemVerilog

Question

I'm trying to connect between a top level module and a program block in SystemVeilog using interface.

I succeed in passing the wires, but I couldn't do it also for the parameters.

How can I pass the parameters in the module to the program? Is it possible in any way?

Answer 1

You pass a parameter to a program in the same way as you pass one to a module . Refer to the IEEE Std 1800-2012, Section "24. Programs". For example:

module tb;
    test #(.WIDTH(8)) test ();
endmodule

program test;
    parameter WIDTH = 5;
    initial $display("WIDTH = %0d", WIDTH);
endprogram

Output:

WIDTH = 8