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Makefile中的相应依赖项和目标列表

[英]Corresponding dependency and target lists in Makefile

In a makefile, suppose I have two corresponding dependency and target lists, like this: 在一个makefile中,假设我有两个对应的依赖项和目标列表,如下所示:

SRC = x.c y.c z.c
OBJS = x.o y.o z.o

Of course, my example is more complicated than this, but I want to know if it is possible to automatically create targets xo, yo, zo depending on xc, yc, zc respectively, like this: 当然,我的示例比这更复杂,但是我想知道是否有可能分别根据xc,yc和zc自动创建目标xo,yo,zo,如下所示:

x.o: x.c
y.o: y.c
z.o: z.c

You can use substitution references : 您可以使用替代引用

OBJS = $(SRC:.c=.o)

or patsubst : patsubst

OBJS = $(patsubst %.c,%.o,$(SRC))

I think the question was how to create rules for each of these targets, not how to create OBJS from SRC (although it's good to do that!). 我认为问题是如何为每个目标创建规则,而不是如何从SRC创建OBJS (尽管这样做很好!)。

The simplest way is to use the already-built-in rule in make that knows how to do it; 最简单的方法是在已经知道如何执行的make中使用内置规则。 you don't need to write your own. 您不需要自己编写。 Just use: 只需使用:

all: $(OBJS)

and they'll all be created. 它们都将被创建。 You can control the compiler by setting the CC variable, the preprocessor flags by setting the CPPFLAGS variable, and the other compiler flags by setting the CFLAGS variable. 您可以通过设置CC变量,通过设置CPPFLAGS变量的预处理器标志以及通过设置CFLAGS变量的其他编译器标志来控制编译器。

If you DO really want to write your own rule, then pattern rules will do that for you easily: 如果您确实想编写自己的规则,那么模式规则将为您轻松做到这一点:

%.o : %.c
        $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

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