[英]Verilog testbench code using gEDA and iVerilog
My assignment is to code a simple 2 to 4 decoder and then display the possible outcomes and waveform.我的任务是编写一个简单的 2 到 4 解码器,然后显示可能的结果和波形。
I am using the gEDA suite along with Icarus Verilog (iVerilog) as a compiler and GTKWave for the waveform.我使用 gEDA 套件和 Icarus Verilog (iVerilog) 作为编译器和 GTKWave 作为波形。
This is my first time coding with Verilog or working with the gEDA suite.这是我第一次使用 Verilog 编码或使用 gEDA 套件。 From googling it appears I need to follow this designflow:
从谷歌搜索看来,我需要遵循这个设计流程:
The testbench file wont compile and I am not sure why, I have tried several variations and I keep getting errors.测试台文件无法编译,我不知道为什么,我尝试了几种变体,但不断出现错误。 Any help is much appreciated.
任何帮助深表感谢。 Thank you.
谢谢你。
Here is my design file code:这是我的设计文件代码:
// 2 to 4 Decoder
// File Name: decoder.v
module decoder(X,Y,E,Z);
input X,Y,E;
output [0:3]Z;
wire [0:3]Z;
wire X1, Y1;
not
inv1(X1,X),
inv2(Y1,Y);
and
and1(Z[0],X1,Y1,E),
and2(Z[1],Y1,X,E),
and3(Z[2],Y,X1,E),
and4(Z[3],X,Y,E);
endmodule
Here is my testbench code:这是我的测试平台代码:
module decoder_tb;
input X,Y,E;
output [0:3]Z;
//wire [0:3]Z;
//wire X1, Y1;
// should create .vcd dump file for GTKWave
initial
begin
$dumpfile("decoder.vcd");
$dumpvars();
end
decoder decode(X,Y,E,Z);
initial
begin
$display($time,"<< Z[0]=%d Z[1]=%d Z[2]=%d Z[3]=%d >>", Z[0] , Z[1] , Z[2] , Z[3] );
end
initial
begin
#0
X = 0; Y = 0; E = 1;
#5
X = 0; Y = 1; E = 1;
#10
X = 1; Y = 0; E = 1;
#15
X = 1; Y = 1; E = 1;
end
endmodule
The commands in terminal I am using are:我正在使用的终端中的命令是:
iverilog -o decoder.vvp decoder.v decoder_tb.v
gtkwave decoder.vcd
EDIT: Here is the exact error message编辑:这是确切的错误消息
aj@aj:~/verilogCode$ iverilog -o decoder.vvp decoder.v decoder_tb.v
decoder_tb.v:26: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6: : X is declared here as wire.
decoder_tb.v:26: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6: : Y is declared here as wire.
decoder_tb.v:26: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6: : E is declared here as wire.
decoder_tb.v:28: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6: : X is declared here as wire.
decoder_tb.v:28: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6: : Y is declared here as wire.
decoder_tb.v:28: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6: : E is declared here as wire.
decoder_tb.v:30: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6: : X is declared here as wire.
decoder_tb.v:30: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6: : Y is declared here as wire.
decoder_tb.v:30: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6: : E is declared here as wire.
decoder_tb.v:32: error: X is not a valid l-value in decoder_tb.
decoder_tb.v:6: : X is declared here as wire.
decoder_tb.v:32: error: Y is not a valid l-value in decoder_tb.
decoder_tb.v:6: : Y is declared here as wire.
decoder_tb.v:32: error: E is not a valid l-value in decoder_tb.
decoder_tb.v:6: : E is declared here as wire.
12 error(s) during elaboration.
In your testbench, change input
to reg
and output
to wire
.在您的测试平台中,将
input
更改为reg
并将output
更改为wire
。 This fixes the compile errors for me (although, I am not using gEDA or iVerilog):这为我修复了编译错误(尽管我没有使用 gEDA 或 iVerilog):
module decoder_tb;
reg X,Y,E;
wire [0:3]Z;
My simulators gave much more meaningful error messages than yours in this case:在这种情况下,我的模拟器给出了比你更有意义的错误信息:
Identifier 'X' does not appear in port list.
标识符“X”未出现在端口列表中。
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