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Verilog测试台比较

[英]Verilog testbench comparison

I have the results of five circuit simulations with some tests, and the result is to be noted in a fault table. 我有五个电路仿真的结果和一些测试,结果将在故障表中注明。

Now I have to compare the values generated from a new circuit with the values that I already have from the above circuit simulations. 现在,我必须将新电路生成的值与上述电路仿真中已有的值进行比较。 I am doing this so to know from which fault class does my new circuit is. 我这样做是为了知道我的新电路是哪个故障类。

How do I store the value of my previous simulations in the testbench and how do I compare my new values to the previous stored results in the same testbench and the fault class it matches I have to print that fault class? 如何将以前模拟的值存储在测试平台中,如何将新值与先前存储的结果在同一测试平台中进行比较,以及它匹配的故障类我必须打印该故障类?

So basically I want to know how to do comparison. 所以基本上我想知道如何进行比较。

One easy way is to dump the values you are interested in in a text file. 一种简单的方法是将您感兴趣的值转储到文本文件中。 You can time stamp (or print the clock cycle number) at each line. 您可以在每一行标记时间戳(或打印时钟周期数)。 A simple diff, perl script or programs like meld and WinMerge can be used to compare the two files and to find out at what time or on which clock cycles the values are different. 可以使用简单的diff,perl脚本或meld和WinMerge等程序来比较这两个文件,并找出值在不同的时间或时钟周期。

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