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Question

`timescale 1ns / 1ps

module test_module_t( 
     input              clk_net,
     /* Network interfaces */                   
     input      [63:0]  rx_data_net,
     input              rx_sof_net,
     input              rx_eof_net,
     input              rx_vld_net,
     output reg [31:0]  port_match=0
    );
    
always @(posedge clk_net) begin
    if(rx_vld_net && rx_sof_net)
        port_match <= 0;
    else if(rx_vld_net)
        port_match <= port_match+1;
    if (rx_vld_net && rx_eof_net)
        port_match <= 0;
end

endmodule


module test_module_tb;

reg         clk_net_tb = 0;
reg  [63:0] rx_data_net_tb;
reg         rx_sof_net_tb;
reg         rx_eof_net_tb;
reg         rx_vld_net_tb;

wire [31:0]  port_match_tb = 0;

integer i;

always #0.5  clk_net_tb = ~clk_net_tb;

initial  begin : full_packet
  
    rx_eof_net_tb = 1'b0;
    rx_sof_net_tb = 1'b0;
    rx_vld_net_tb = 1'b0;
    rx_data_net_tb = 64'h0000000000000000;
    #10

    rx_eof_net_tb = 1'b0;
    rx_sof_net_tb = 1'b1;
    rx_vld_net_tb = 1'b0;
    rx_data_net_tb = 64'h0000a94d00000000;   
    #1;
    
    rx_vld_net_tb = 1'b1;
    #1;
    
    rx_sof_net_tb = 1'b0;
    rx_vld_net_tb = 1'b0;
    rx_eof_net_tb = 1'b0;
    rx_data_net_tb = 64'h00000000002d0000;
    #1
    
    rx_vld_net_tb = 1'b1;
    #1
    
    rx_sof_net_tb = 1'b0;
    rx_vld_net_tb = 1'b0;
    rx_data_net_tb = 64'hdeadbeef;
    #1
    
    rx_vld_net_tb = 1'b1;
    #1
    
    rx_eof_net_tb = 1'b1;
    rx_vld_net_tb = 1'b0;
    rx_data_net_tb = 64'h000decaf;
    #1
    
    rx_vld_net_tb = 1'b1;
    #1
    
    rx_eof_net_tb = 1'b0;
    rx_vld_net_tb = 1'b0;   
    rx_data_net_tb = 64'h0000000000000000; 
    $stop;
end

       test_module_t test_module_i
       (
        .clk_net(clk_net_tb),
        .rx_sof_net(rx_sof_net_tb),
        .rx_vld_net(rx_vld_net_tb),
        .rx_data_net(rx_data_net_tb),
        .rx_eof_net(rx_eof_net_tb),
        .port_match(port_match_tb)
       );
    
endmodule

This is the code I have been working on. The signal in test_module: port_match updates correctly, but the same signal value is not reflected in the testbench. port_match_tb value goes x when testing.

Attaching a screenshot of the simulation of the above code. If anybody could help me out with where this is going wrong.

Answer 1

The port_match_tb wire has multiple drivers: the wire declaration where you continuously drive it as 0, and the test_module_t output. Change:

wire [31:0]  port_match_tb = 0;

to:

wire [31:0]  port_match_tb;

This eliminates the x and allows port_match_tb to match port_match .