Verilog testbench comparison

Question

I have the results of five circuit simulations with some tests, and the result is to be noted in a fault table.

Now I have to compare the values generated from a new circuit with the values that I already have from the above circuit simulations. I am doing this so to know from which fault class does my new circuit is.

How do I store the value of my previous simulations in the testbench and how do I compare my new values to the previous stored results in the same testbench and the fault class it matches I have to print that fault class?

So basically I want to know how to do comparison.

Answer 1

One easy way is to dump the values you are interested in in a text file. You can time stamp (or print the clock cycle number) at each line. A simple diff, perl script or programs like meld and WinMerge can be used to compare the two files and to find out at what time or on which clock cycles the values are different.