(Verilog) Testbench Wait

Question

I am having problems with creating a testbench for my adders. When I start the testbench it will assign the initial start time as t1 and input a and b and when cout is a 1 it will set the final time to t2 . Finally the delay is the subtraction of t2 and t1 .

The problem is mostly syntax errors.

This is my code so far:

parameter N = 16;
parameter A = 0;

reg[N-1:0] a, b;
wire[N-1:0] sum;
reg cin;
wire cout;

arith_unit #(.ADDER_TYPE(A), .WIDTH(N)) tb (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));
initial begin
a = 0;
b = 0;
cin = 0;
#50;


$time(t1);

a = 16'b0010110110100010;
b = 16'b1011111101100111; 
cin = 1'b0;

wait (if (cout == 1)) $time(t2); <-------sytax error here

int delay = t2 - t1; <-------sytax error here

$display ("%d", delay);
end
endmodule

Thank you for the help.

Answer 1

• wait (if (cout == 1)) should be wait (cout == 1) .

• int doesn't exist as a variable type in Verilog (it does in SystemVerilog). I think you want integer or time . Also note that a variable can not be created simply anywhere. In Verilog, it needs to declared with your reg and wire declarations.

• $time doesn't take arguments. Use t1 = $time;

• t1 and t2 are not declared. Perhaps integer or time .

Unless you have some delay inside arith_unit the delay will be 0. If there is delay, you may want to double check that cout is glitch free as wait cannot distinguish between glitches and stable signals.