I have inherited a Lattice Diamond project. Things seem to be fine, excpet for the systems constraints file. In the Lattice Diamon file list, the sdc ...
I have inherited a Lattice Diamond project. Things seem to be fine, excpet for the systems constraints file. In the Lattice Diamon file list, the sdc ...
In a Lattice Verilog FPGA design, I have two PLL-generated clocks at the same frequency 125MHz (8ns) but the second clock is at 90° shift of the first ...
I’m new to TinyFPGA, so I need a little help! I’m working on a Tiny FPGA project for sensors and actuators where each tinyFPGA provides an 8 bit digit ...
I have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to imp ...
Please could someone explain to me what could be the cause of this error : ERROR - logical net 'd0_ch1_n_i' has both active and tristate drivers. ...
I'm trying to make a Blink-LED program for a Lattice MachXO3L breakout board. I believe I have the internal-oscillator set up, I just don't know how t ...
I have a design where I use an IP module generated by Lattice Diamond. This uses the Macxo3l library which is shipped with diamond as a vendor library ...
What is the effect of configuring a pull mode on a pin designated as output in the synthesis? Does the pull mode still take effect? Is its use onl ...
I have a MachXO3 chip. Family datasheet is available here: http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/DS1047-MachXO3 ...
I've written a VHDL design that halves the clock's frequency and outputs this 'data clock' onto the sclk pin. I also have a data pin called 'sda' that ...
edit: I just reinstalled lattice diamond and the updates, Active-hdl was installed automatically, but the simulation still gives me the same error. wh ...
Why does Lattice Diamond shows Error 9 on a new project when compiling? Error output is: It works on one project, not on this one! ...
I have a lattice MachXO3L starter kit and I'm having some trouble with inputs, I think. I'm tried reducing the code only to read 4 switches (MachXO3 S ...
I am using Lattice Diamond and I have a verilog file with a bunch of `define statements to define global constants. I include this "header" file into ...
install Lattice Diamond 3.10 on my computer with Manjaro 17.1 and everything works correctly just because of a problem. The programming tool does not ...
I'm using active-hdl to simulate my FPGA designs and I'd like to know if it's possible to use dynamically generated strings to represent my signals in ...
I am attempting to learn VHDL and as an exercise I am trying to construct a very simple serial port that uses RS-232 style signalling (8N1 format). H ...
I'm reading initial RAM values for a 4 KiB (1Ki x 32-Bit) True-Dual-Port RAM from disk. Because my Lattice ECP5 devices has only 18-bit wide Embedded ...
I have a Lattice Diamond project for an SPI multiplexer, which has the following module definition: When I go into the Spreadsheet View to assign m ...
I am attempting to create a time delay that will synthesize, and not just work in my simulation. The delay needs to be 1.439548 ms or as close as poss ...