I want to slice a std_logic_vector in VHDL obtaining parts of it of fixed dimensions. The general problem is: din N*M bits dout M bits sel clog2 ...
I want to slice a std_logic_vector in VHDL obtaining parts of it of fixed dimensions. The general problem is: din N*M bits dout M bits sel clog2 ...
I have this code for a ram in VHDL and I get the following error while synthesis: Error (10818): Can't infer register for "data_table[19][13]" at RAM ...
I have packaged an IP and in its top module I have a constant array of std_logic_vector for some purpose. If I need to use only a single instance of t ...
Let's say I have the following: Is there a general way in VHDL-2008 to specify the conversion between any of these types without defining conversio ...
I am using external naming to instantiate the following code: As you can see, there is a lot of duplication in my referencing. Is there a way to do ...
I want an approximation of the Tanh function by saving the values in a LUT (by this I am doing a quantization). I want to choose the Number of entries ...
I want to do an code, which accumulates an input signal. This means the input signal is added to the previous value. This is then the output The pr ...
I wrote a code. This should insert a "1" at a position, which is determined by the binary part of a signal E_reg_sig. The bits left to the "1" should ...
I am trying to exclude certain vhdl files from my code coverage report, but I can't get it to work. My report always shows all available files. My wo ...
I got the warning "[Synth 8-6014] Unused sequential element MVM_RST_reg was removed. " I am a little bit confused, because the signal is connected and ...
I want to convert a real number to his bit representation, with the fields of sign, exponent and mantissa in a VHDL TB for testing purposses (as a STD ...
I've this error on my code at the line 13 and 27, on vhdl, do anyone know what's wrong? I tried on other computers and compilers, and all got the s ...
I am new to VHDL, so I have developed some code for a Ring Oscillator using the internal clock of my board, but I want to add a 2nd One using the inte ...
I have a Module consisting from another module. e.g. The logic behind this is I have several other modules connected to reset (not shown in this ex ...
I have my simple code in VDHL that seperates digit from 2-digit number, but when testing, my seperated digits remain unsigned (u). I have a hunch that ...
I have declared an array For simulation, I want to display the array as integer-numbers So I created and But it fails. How to convert it? Do ...
Please forgive myself if you will find some trivial errors in my code .. I'm still a beginner with VHDL. Well, I have to deal with a serial interface ...
I am really confused, because it is a simple code and I dont find the error. Syntax is fine, but in Simulation the Values of Dready and acc_value dont ...
Trying to design a simple MAC Unit in VHDL Seems like there is a problem with acc_value := (acc_value + WEIGHT* DIN); . There is an error in the s ...
I did a counter like i normally do on VHDL (Modelsim) and when i simulate my code with my testbench all the counters do not work at all. They stay at ...