VHDL-2008 External Naming Compaction

Question

I am using external naming to instantiate the following code:

  snapshot_inst : entity work.snapshot
  port map (
    clk => clk_400,
    
    resampler0_data_i => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_timing_i : slv16_array(1 downto 0) >>,
    resampler1_data_i => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_timing_i : slv16_array(1 downto 0) >>,
    resampler2_data_i => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_timing_i : slv16_array(1 downto 0) >>,
    resampler0_data_q => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_timing_q : slv16_array(1 downto 0) >>,
    resampler1_data_q => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_timing_q : slv16_array(1 downto 0) >>,
    resampler2_data_q => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_timing_q : slv16_array(1 downto 0) >>,
    resampler0_valid  => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_timing_valid : std_logic >>,
    resampler1_valid  => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_timing_valid : std_logic >>,
    resampler2_valid  => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_timing_valid : std_logic >>,
    
    equalizer0_data_i => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_eq_i : std_logic_vector(15 downto 0) >>,
    equalizer1_data_i => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_eq_i : std_logic_vector(15 downto 0) >>,
    equalizer2_data_i => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_eq_i : std_logic_vector(15 downto 0) >>,
    equalizer0_data_q => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_eq_q : std_logic_vector(15 downto 0) >>,
    equalizer1_data_q => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_eq_q : std_logic_vector(15 downto 0) >>,
    equalizer2_data_q => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_eq_q : std_logic_vector(15 downto 0) >>,
    equalizer0_valid  => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_eq_valid : std_logic >>,
    equalizer1_valid  => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_eq_valid : std_logic >>,
    equalizer2_valid  => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_eq_valid : std_logic >>,
    
    phased0_data_i    => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_carrier_i : std_logic_vector(15 downto 0) >>,
    phased1_data_i    => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_carrier_i : std_logic_vector(15 downto 0) >>,
    phased2_data_i    => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_i : std_logic_vector(15 downto 0) >>,
    phased0_data_q    => << signal demod_deframe_gen(0).demod_inst.u_demod.ext.ext_carrier_q : std_logic_vector(15 downto 0) >>,
    phased1_data_q    => << signal demod_deframe_gen(1).demod_inst.u_demod.ext.ext_carrier_q : std_logic_vector(15 downto 0) >>,
    phased2_data_q    => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_q : std_logic_vector(15 downto 0) >>,
    phased0_valid     => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_valid : std_logic >>,
    phased1_valid     => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_valid : std_logic >>,
    phased2_valid     => << signal demod_deframe_gen(2).demod_inst.u_demod.ext.ext_carrier_valid : std_logic >>,
    
    up_bus_in         => up_bus_in,
    up_bus_out        => up_bus_outs(9)
  );

As you can see, there is a lot of duplication in my referencing. Is there a way to do something like:

alias demod(x) is demod_deframe_gen(x).demod_inst.u_demod.ext -- Aliases a block, not a signal

That way I can shorten all of my external naming references?

Answer 1

What the OP is looking for is something to abstract and simplify the external_pathname of an external name.

If it were supported by VHDL, it could look something like the following, however, this fails both the OP's example in Xilinx and my test case (which requires a "." as the first path element).

alias demod0 is demod_deframe_gen(0).demod_inst.u_demod.ext ;
alias demod1 is demod_deframe_gen(1).demod_inst.u_demod.ext ;
alias demod2 is demod_deframe_gen(2).demod_inst.u_demod.ext ;

. . . 

  snapshot_inst : entity work.snapshot
  port map (
    clk => clk_400,
    
    resampler0_data_i => << signal demod0.ext_timing_i : slv16_array(1 downto 0) >>,
    resampler1_data_i => << signal demod1.ext_timing_i : slv16_array(1 downto 0) >>,
    resampler2_data_i => << signal demod2.ext_timing_i : slv16_array(1 downto 0) >>

There is no question that a capability of this sort is needed in the language. I have added it to the following VHDL language issue: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/115