Error (10818): Can't infer register because it does not hold its value outside the clock edge, how to fix it?

Question

I have this code for a ram in VHDL and I get the following error while synthesis:

Error (10818): Can't infer register for "data.table[19][13]" at RAM.vhd(50) because it does not hold its value outside the clock edge

any help would be appreciated!

here is the code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RAM is
    port (
    clk, wr_en : in std_logic;
        address: in std_logic_vector (9 downto 0);
        data_in : in std_logic_vector (15 downto 0);
    data_out: out std_logic_vector (15 downto 0)
  );
end entity RAM;

architecture RAM_Arch of RAM is
    type Memory is array (0 to 1023) of std_logic_vector (15 downto 0);
  signal data_table : Memory := (others => (others => '0'));

begin
    process (clk)
        variable init : boolean := true;

    begin
        if init = true then
            -- some initiation
            data_table(0) <= "0001010000011010";
            data_table(1) <= "0011110000001000";
            data_table(2) <= "0011110000010000";
            data_table(3) <= "0011110000100000";
            data_table(4) <= "0011110000000001";
            data_table(10) <= "0001010000011100";
      data_table(11) <= "0100000000000001";
      data_table(12) <= "0011110000000001";
      data_table(13) <= "0011110000000010";
      data_table(14) <= "0011110000000100";
      data_table(15) <= "0011110000001000";
      data_table(16) <= "0011110000010000";
      data_table(17) <= "0011110000100000";
      -- data_table(18) <= "0011110001000000";
      data_table(19) <= "1011110000010000";
      -- data_table(19) <= "1011110000000001";
      -- data_table(20) <= "1011110000000010";
      -- data_table(21) <= "1011110000000100";
      -- data_table(22) <= "1011110000001000";
      -- data_table(24) <= "1011110000100000";
      -- data_table(25) <= "1011110001000000";
      -- data_table(26) <= "1011110010000000";
            init := false;
        end if;

        if  clk'event and clk = '1' then
            if wr_en = '1' then -- Writing :)
               data_table(to_integer(unsigned(address))) <= data_in;
      end if;
        end if;
    end process;

  data_out <= data_table(to_integer(unsigned(address)));

end architecture RAM_Arch;

Answer 1

If your code must be synthesized never put non-synchronous assignments in a synchronous process. Try:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram is
  port (
    clk, wr_en: in std_logic;
    address:    in std_logic_vector(9 downto 0);
    data_in :   in std_logic_vector(15 downto 0);
    data_out:  out std_logic_vector(15 downto 0)
  );
end entity ram;

architecture ram_arch of ram is

  type memory is array (0 to 1023) of std_logic_vector (15 downto 0);
  signal data_table: memory := (
     0 => "0001010000011010",
     1 => "0011110000001000",
     2 => "0011110000010000",
     3 => "0011110000100000",
     4 => "0011110000000001",
    10 => "0001010000011100",
    11 => "0100000000000001",
    12 => "0011110000000001",
    13 => "0011110000000010",
    14 => "0011110000000100",
    15 => "0011110000001000",
    16 => "0011110000010000",
    17 => "0011110000100000",
    -- 18 => "0011110001000000",
    19 => "1011110000010000",
    -- 19 => "1011110000000001",
    -- 20 => "1011110000000010",
    -- 21 => "1011110000000100",
    -- 22 => "1011110000001000",
    -- 24 => "1011110000100000",
    -- 25 => "1011110001000000",
    -- 26 => "1011110010000000",
    others => (others => '0'));

begin

  process (clk)
  begin
    if rising_edge(clk) then
      if wr_en = '1' then -- writing :)
        data_table(to_integer(unsigned(address))) <= data_in;
      end if;
    end if;
  end process;

  data_out <= data_table(to_integer(unsigned(address)));

end architecture ram_arch;

Note: you should probably not use std_logic . If you do not know the difference with std_ulogic prefer the latter. Same with std_logic_vector : prefer std_ulogic_vector .