VHDL Code Error: “Error (10818): Can't infer register for <name> at <location> because it does not hold its value outside the clock edge”

Question

I know this error has been encountered several times on SO, but as a beginner I am still unable to see how to solve this error in my own code. The error and code are both printed below, thank you to anyone for their input.

Error (10818): Can't infer register for count[0] at 5bit_PHreg_vhdl.vhd(21) because it does not hold its value outside the clock edge

The error is repeated for each bit of 'count' and refers to the line noted in the code.

ARCHITECTURE behavioral OF 5bit_PHreg_vhdl IS
SIGNAL count    :   STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN
    PROCESS(reset, clk, SHR_EN)
        BEGIN
-- Check if asynchronous reset is 0
        IF reset = '0' THEN --ERROR OCCURS HERE
                count <= "00000";
-- Check if rising edge
        ELSIF (clk'EVENT AND clk = '1') THEN
                IF LD_EN = '1' THEN
                    count <= FA_in;
                END IF;
-- Check if SHR_EN is active
        ELSIF (SHR_EN = '1') THEN
                count(4) <= c_in;
                count(3) <= count(4);
                count(2) <= count(3);
                count(1) <= count(2);
                count(0) <= count(1);
                c_out <= count(0);
        END IF;
    END PROCESS;
    PH_reg_out <= count;
END behavioral;

Answer 1

ELSIF (SHR_EN = '1') THEN is outside the reset and clock edge conditions, it's form not recognized for synthesis.

Move it and the following assignments inside the preceding end if so it's registered. Remove SHR_EN from the process sensitivity list.

Also in VHDL a name can't start with a number, 5bit_PHreg_vhdl is invalid as an entity name.

Fixing these and filling in the missing entity declaration:

library ieee;
use ieee.std_logic_1164.all;

entity PH_reg_5_bit is
    port (
        reset:      in  std_logic;
        clk:        in  std_logic;
        LD_EN:      in  std_logic;
        SHR_EN:     in  std_logic;
        FA_in:      in  std_logic_vector (4 downto 0);
        c_in:       in  std_logic;
        c_out:      out std_logic;
        PH_reg_out: out std_logic_vector (4 downto 0)
    );
end entity;

ARCHITECTURE behavioral OF PH_reg_5_bit IS
    SIGNAL count    :   STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN
    PROCESS (reset, clk) -- , SHR_EN)
        BEGIN
-- Check if asynchronous reset is 0
        IF reset = '0' THEN --ERROR OCCURS HERE
                count <= "00000";
-- Check if rising edge
        ELSIF (clk'EVENT AND clk = '1') THEN
                IF LD_EN = '1' THEN
                    count <= FA_in;
        -- Check if SHR_EN is active
                ELSIF (SHR_EN = '1') THEN
                        count(4) <= c_in;
                        count(3) <= count(4);
                        count(2) <= count(3);
                        count(1) <= count(2);
                        count(0) <= count(1);
                END IF;
-- -- Check if SHR_EN is active
--         ELSIF (SHR_EN = '1') THEN
--                 count(4) <= c_in;
--                 count(3) <= count(4);
--                 count(2) <= count(3);
--                 count(1) <= count(2);
--                 count(0) <= count(1);
--                 c_out <= count(0);
        END IF;
    END PROCESS;

    c_out <= count(0);  -- c_out not separately registered
    PH_reg_out <= count;
END behavioral;

and your code analyzes successfully.

The entity name is a good indication you haven't simulated your design.

Note the order of conditions implies loading has priority over shifting.

I'd suspect c_out should not be registered allowing shift register instances to be concatenated into a larger shift register using c_in and c_out. This means it's assignment should be outside the if statement containing the clock edge event, it can go next to the other output pin assignment.