I am new to VHDL, so I have developed some code for a Ring Oscillator using the internal clock of my board, but I want to add a 2nd One using the inte ...

I want to make communication using Altera MM Mailbox IP component, between Aria V hps and my nios processors. Project in Qsys I managed to write dow ...

I'm sending this to the server: I get back a string of data like this: On the website it lists a variable length structure typedef struct Zones ...

I need to implement a watchdog timer on my Cyclone II FPGA board. I have designed the system using QSYS, i need to know what are the next steps to imp ...

I am doing a project using DE1-SoC (FPGA + ARM cortex A9). You can see a part of the design (Qsys, platform designer) here An on chip memory (RAM, im ...

There is pretty much exhaustive info about tables (PF including PF-SRC,LF etc) resides in QSYS2.SYSTABLES. However when it comes to enumerating all o ...

I fetched and built the linux-socfpa for my Altera DE2-115. I used buildroot and u-boot to build it. It starts but there is no filesystem. I have an S ...

I am looking for HPS to FPGA custom component integrations guideline using Qsys. I have De0 nano SoC board. I am new to SoC FPGA programming. I still ...

I'm using a design in Qsys to run uClinux v2.6. I would like to run a newer Linx but I wa told that I must change the Qsys design and add another ...

I want to make a simple project on which I load 10 numbers in SDRAM of my Altera DE1-SOC ready to be taken as input for a Logic Unit I am creating, ...

I having some issues with generating SPI master core in qsys. I opened a clean design (with no core in it), and added the SPI core to it and exported ...

I want to transfer a fork-join problem in fpga. Fork-join in the sense that there will be many small components (> 100) accessing a memory componen ...

I have a custom QSys component, that instantiates a couple of Altera IP. The Altera IP is also in the form of .qsys files. Is it possible to have Qsys ...

In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Mas ...

For reasons which cannot be avoided (requirements of Qsys), I have several Verilog modules which end up with many ports which would be far easier to w ...

Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component w ...

I am trying to make some tests with an FPGA and while trying to add an UART to my design using the Quartus II v13.0 SP1 and the Megawizard plug-in I r ...

Is it possible to do DMA transferts with the IP core «Cyclone V Avalon-MM for PCIe» provided by altera in Qsys (quartus 14.0) ? Altera provide an ip- ...

Is it possible to modify Verilog generated by Qsys before Quartus synthesis ? I designed a component under Qsys. I added the design.qsys file under m ...

When trying to assemble the system according to the instructions in this document http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf I ge ...