I can't understand how the device tree information is used in a specific driver. This is a code snippet from linux-6.15.68 drivers/pci/controller/dwc/ ...
Some CPU like x86 processor has two address spaces. One for memory and one for IO. And different instructions to access them. And the PCI 3.0 spec al ...
do integrated GPUs in CPUs have the overhead of transferring data over the PCIe bus just like transferring data between CPU and dedicated GPU? I ask ...
In linux-5.15.68 source tree, I tried to search for the definition of function 'pci_write_config_dword' and this was calling 'pci_bus_write_config_dwo ...
I'm trying to reading PCI CSR (Configuration Space Register) on my system via open,mmap /dev/mem. I met some problems when using 8 byte length readin ...
I want to understand how a CPU works and so I want to know how it communicates with a PCIe card. Which instructions does the CPU use to initialize a ...
Is it possible to issue a prefetch for an address backed by an MMIO region in a PCIe BAR (and mapped via either UC or WC page table entries)? I am cur ...
Is there a way to obtain the physical base address of PCIe ECAM space under Linux (e.g., via sysfs or dmesg)? My intention is to use devmem2 to exam ...
I have couple of doubts regarding PCIe device configuration, Generally a PCIe device is uniquely identify with BDF (BUS DEVICE FUNCTION), As per my un ...
I am working in C++ on Windows and trying to develop a tool that can identify which PCI slots are in use. I can read PCI config space to find the PCI ...
I am attempting to configure the PCIe x4 connection on my ROCKPro64 (RK3399 processor) development board to act as a PCIe endpoint device. My goal is ...
I have a PCIe endpoint device connected to the host. The ep's (endpoints) 512MB BAR is mmapped and memcpy is used to transfer data. Memcpy is quite sl ...
I am developing a driver for PCI Express in Windows environment. I use Windows7 and Windows10 and the HW is i7-7700K, RAM: 16GBytes. There is no prob ...
I was creating some drivers and I found my self stuck in the IRQ Pins, my kernel uses IOAPIC and I don't know how this interrupt mechanism (IRQ Pins) ...
I want to detect the AMD gpu deneration in python code. My case is that to run specific application (davinci resolve), it is required to use amdgpu pr ...
I am working on implementing an FPGA PCIe endpoint to prototype the interface for one project. The FPGA platform I am using is Synopsys HAPS DX7 S6 f ...
I have a ConnectX-6 Infiniband/VPI Adapter. I can setup the hardware rate limit when creating a qp like this: But I cannot dynamically change the q ...
I'm trying to connect a PCIe device to a chipyard design using the existing edge overlay for the VCU118 (slightly modified because I'm using a differe ...
Operating System: RHEL Centos 7.9 Latest Operation: Sending 500MB chunks 21 times from one System to another connected via Mellanox Cables. (Ethernet ...
is there any library or something in C lang, so I can find out Max payload size of PCIe bus ? I think BIOS should know it, is there any chance how to ...