I am trying to add a custom instruction to a freedom e300 rocket-chip. The custom instruction is to perform an operation using the values of register ...

I am trying to use PMP on a 16-byte region to protect a specific memory region. However, I am getting an instruction access fault when jumping to U mo ...

I'm trying to add a new blackboxed verilog module to the chipyard hardware generation framework and simulate it with verilator. My changes pass chipy ...

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I am trying to write a 64 bit word to the MMIO register using the reg_write64 construct defined in mmio.h. Everything works fine as long as the wire t ...

I'm trying to connect a PCIe device to a chipyard design using the existing edge overlay for the VCU118 (slightly modified because I'm using a differe ...

I initialized two registers in my accelerator like If I have loaded a data to my rs1(R-type instruction) in my C test code, I wanted to assign this ...

I have successfully added and simulated my MMIO perihperal coupled to a normal sized rocket core before. But now I want to try to add it to a small co ...

I am trying to build a minimal example, of how to generate an AXI4Stream interface using Chisel and diplomacy. I am using the diplomatic interface alr ...

I want to run a program on Rocket core and observe all the signals in corresponding registers in GTKwave (e.g. PC, register file, ALU registers and wi ...

I'm basing this off of Rocket-chip's implementation of CLINT. I don't believe this is in the RISC-V spec but the notion of CLINT shows up in a lot of ...

I am trying to add an accelerator to the rocket chip framework through the MMIO peripheral. I went through the GCD example and was able to build the b ...

I'm attempting to do these rather large DMA transfers over the frontbus to memory. The frontbus is ready and no other clients are contending for the f ...

I am trying to implement a Rocket chip SoC design; the SoC design will generate an AXI memory port by default. But I want to use the AHB memory port, ...

I have a Module monit which has an parameter threshold , then I want to generate serval(e.g.8) Module monit in the wrapper with different threshold . ...

I was trying to understand the implementation of the AsyncQueue in the RocketChip , and quite puzzled by the use of option method on Boolean data type ...

I would like to increase the number of AsIDBits in the Rocket-Chip from zero to eight and was wondering how that could be accomplished. tile/BaseTile ...

In LazyModule.scala , function AutoBundle() flip the Data(bundleIn) in dangleIn with flipped = true to make autoIO, while in Nodes.scala , function ma ...

I tried using Mem(1024,UInt(width=xLen)); but after synthesizing generated verilog file in Xilinx vivado.The memory mapped as distributed ram. It's re ...

I am trying to find a clean way to access the regmap that is used with *RegisterNode for creating documentation and testing files. The TLRegisterNode ...